Subrata Banik cb8849b686 soc/intel/skylake: Fix SATA booting to OS issue ... SATA device remains unrecognized if connected at Port 2. Port control and Status register (PCS) is by default set by hardware to the disabled state as a result of an initial power on reset. OS read PCS register during boot causes disabling of SATA ports and can't detect any devices. BRANCH=none BUG=chrome-os-partner:59335 TEST=Build and boot SKL from SATA device connected at Port 2. Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-11-07 20:11:43 +01:00
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apollolake	soc/intel/apollolake: Implement SPI flash status register read	2016-11-03 05:36:03 +01:00
baytrail	lib/prog_loaders: use common ramstage_cache_invalid()	2016-10-31 19:34:20 +01:00
braswell	Makefile.inc: Use $(MAINBOARDDIR)	2016-09-04 05:33:25 +02:00
broadwell	lib/prog_loaders: use common ramstage_cache_invalid()	2016-10-31 19:34:20 +01:00
common	soc/intel/common: log event when MRC cache is updated	2016-11-06 18:14:29 +01:00
fsp_baytrail	fsp_baytrail: Refactor code for SPI debug messages	2016-09-06 21:17:59 +02:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled	2016-10-09 19:08:07 +02:00
quark	soc/intel/quark: Fix FSP 2.0 build	2016-09-30 01:16:51 +02:00
sch	src/soc: Remove unnecessary whitespace before "\n" and "\t"	2016-08-28 18:25:14 +02:00
skylake	soc/intel/skylake: Fix SATA booting to OS issue	2016-11-07 20:11:43 +01:00