coreboot-kgpe-d16/src/northbridge
Rudolf Marek cc1e645248 Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3.
The patch looks at certain DDR configurations (dual rank/single rank) and lowers the clocks to 2T or frequency as guide suggest. It sets the DualDIMMen bit which I believe should be set for non-dual channel configs.

The patch does not implement support for three dimm configurations supported from revE.
On the other hand it should improve greatly memory stability across the 939 platform.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 20:43:33 +00:00
..
amd Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3. 2010-12-13 20:43:33 +00:00
intel Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well. 2010-12-13 19:59:13 +00:00
via We hardcode highmemory size in every northbridge! This is bad, and especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic. 2010-12-13 19:50:25 +00:00
Kconfig Drop remainders of PPC port 2009-10-28 19:40:46 +00:00
Makefile.inc Drop remainders of PPC port 2009-10-28 19:40:46 +00:00