coreboot-kgpe-d16/src/soc/intel/braswell
Aaron Durbin cc5ac17fab soc/intel/common: remove chipset specific calls
The report_platform_info() and set_max_freq() are not being
used similarly on skylake and braswell. With the addition
of other SoCs I suspect a similar pattern will emerge. Instead
of having weak functions to ensure things link with the hardcoded
policy push these calls into their respective SoC homes.

For parity, both skylake and braswell were updated to be consistent
with the same calls prior to this patch.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. Built braswell.

Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/303334
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11815
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11 23:55:41 +00:00
..
acpi braswell: Switch to using common ACPI _SWS code 2015-09-17 14:23:52 +00:00
bootblock x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
include/soc soc/intel/common: remove chipset specific calls 2015-10-11 23:55:41 +00:00
romstage soc/intel/common: remove chipset specific calls 2015-10-11 23:55:41 +00:00
acpi.c fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
chip.c Braswell: Modify CB to accomodate new FSPv83 2015-10-11 23:55:27 +00:00
chip.h Braswell: Modify CB to accomodate new FSPv83 2015-10-11 23:55:27 +00:00
cpu.c intel/braswell: allow dirty cache line evictions for SMRAM to stick 2015-08-29 07:10:52 +00:00
elog.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
emmc.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
gfx.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
gpio.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
gpio_support.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
hda.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
iosf.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
Kconfig Add EM100 'hyper term' spi console support in ramstage & smm 2015-10-05 17:43:11 +00:00
lpc_init.c Braswell: Update to end of June. 2015-07-06 18:45:23 +02:00
lpe.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
lpss.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
Makefile.inc cpu: microcode: Use microcode stored in binary format 2015-09-30 06:57:19 +00:00
memmap.c intel/common: fix stage_cache_external_region() 2015-08-14 15:19:31 +02:00
northcluster.c fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
pcie.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
placeholders.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
pmutil.c Braswell: Update to end of June. 2015-07-06 18:45:23 +02:00
ramstage.c braswell: Switch to using common ACPI _SWS code 2015-09-17 14:23:52 +00:00
sata.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
scc.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
sd.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
smihandler.c braswell: Tristate CFIO 139 and CFIO 140 2015-09-08 11:48:09 +00:00
smm.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
southcluster.c Braswell: Update the ACPI tables 2015-07-06 18:44:38 +02:00
spi.c Drop "See file CREDITS..." comment 2015-09-07 15:54:50 +00:00
spi_loading.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
tsc_freq.c Braswell: Update to end of June. 2015-07-06 18:45:23 +02:00