Felix Held cc975c5c65 soc/amd/cezanne/Kconfig: select missing SSE2 option ... This will set the corresponding enable bit in CR4 in bootblock_crt0.S Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I648a83fbcb71456bf1e5b11c491e7cadc8e0e281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-01-24 18:16:17 +00:00
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cezanne	soc/amd/cezanne/Kconfig: select missing SSE2 option	2021-01-24 18:16:17 +00:00
common	ACPI: Add helpers for CBMEM_ID_POWER_STATE	2021-01-23 20:31:09 +00:00
picasso	soc/amd/picasso: Remove some empty strings	2021-01-24 18:10:31 +00:00
stoneyridge	soc/amd: Rename chipset_state to chipset_power_state	2021-01-23 20:21:14 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00