coreboot-kgpe-d16/src
Aaron Durbin cd72103021 arm64: remove EL and mode from secmon_params
Since PSCI dynamically determines which EL to transition
to based on SCR_EL3 there's no need to provide that
information.

BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel with MP.

Change-Id: Ia59bc8116ec4ae9bde2e6cad1861f76c14f7d495
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8bc5f7c8a114568ede98478c2fbea2f8b7d97f0c
Original-Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218924
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 08:44:54 +01:00
..
arch arm64: remove EL and mode from secmon_params 2015-03-28 08:44:54 +01:00
console arm64: Add support for secure monitor 2015-03-28 07:05:09 +01:00
cpu cpu/amd/model_10xxx: Increase preram buffer size to 32k 2015-03-25 17:26:48 +01:00
device PCIe: Revise L1 Sub-State support 2015-03-23 13:11:18 +01:00
drivers drivers: add GIC support 2015-03-28 07:05:03 +01:00
ec chromeec: Add ACPI device for PD MCU and handle related EC host event 2015-03-27 06:30:44 +01:00
include arm64: add spin table support 2015-03-28 07:05:13 +01:00
lib arm64: Add support for secure monitor 2015-03-28 07:05:09 +01:00
mainboard Ryu: Move I2C6 init to ramstage 2015-03-28 07:05:39 +01:00
northbridge northbridge/amd/amdfam10: Properly implement SLIT generation 2015-03-27 17:07:06 +01:00
soc Ryu: Move I2C6 init to ramstage 2015-03-28 07:05:39 +01:00
southbridge CBMEM: Add LATE_CBMEM_INIT guards 2015-03-19 06:17:07 +01:00
superio superio: ite8772f: Exit extemp busy state 2015-03-21 08:44:28 +01:00
vendorcode Chrome OS vendorcode: Fix vboot_reference compilation 2015-03-26 03:07:18 +01:00
Kconfig Enable publishing of board ID where supported 2015-03-23 17:20:24 +01:00