3b6c527322
enable may do printk()s which result in a 2 minute delay on some boards. Fix this on all boards which currently do smbus_enable() before enabling the serial console. Thanks to Elia Yehuda <z4ziggy@gmail.com> for tracking this bug down. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
163 lines
3.4 KiB
C
163 lines
3.4 KiB
C
#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#if 0
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#include <cpu/x86/lapic.h>
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#endif
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include <stdlib.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/via/vt8623/raminit.h"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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/*
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*/
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void udelay(int usecs)
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{
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int i;
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for(i = 0; i < usecs; i++)
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outb(i&0xff, 0x80);
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}
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#include "lib/delay.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "lib/debug.c"
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#include "southbridge/via/vt8235/vt8235_early_smbus.c"
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#include "southbridge/via/vt8235/vt8235_early_serial.c"
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static void memreset_setup(void)
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{
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/via/vt8623/raminit.c"
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static void enable_mainboard_devices(void)
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{
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device_t dev;
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_8235), 0);
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if (dev == PCI_DEV_INVALID) {
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die("Southbridge not found!!!\n");
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}
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pci_write_config8(dev, 0x50, 0x80);
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pci_write_config8(dev, 0x51, 0x1f);
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#if 0
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// This early setup switches IDE into compatibility mode before PCI gets
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// a chance to assign I/Os
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// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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// // movb $0x09, %dl
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// movb $0x00, %dl
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// PCI_WRITE_CONFIG_BYTE
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#endif
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/* we do this here as in V2, we can not yet do raw operations
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* to pci!
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*/
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dev += 0x100; /* ICKY */
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pci_write_config8(dev, 0x04, 7);
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pci_write_config8(dev, 0x40, 3);
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pci_write_config8(dev, 0x42, 0);
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pci_write_config8(dev, 0x3c, 0xe);
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pci_write_config8(dev, 0x3d, 0);
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}
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static void enable_shadow_ram(void)
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{
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device_t dev = 0; /* no need to look up 0:0.0 */
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unsigned char shadowreg;
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/* dev 0 for southbridge */
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shadowreg = pci_read_config8(dev, 0x63);
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/* 0xf0000-0xfffff */
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shadowreg |= 0x30;
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pci_write_config8(dev, 0x63, shadowreg);
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}
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static void main(unsigned long bist)
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{
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unsigned long x;
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device_t dev;
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/*
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* Enable VGA; 32MB buffer.
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*/
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pci_write_config8(0, 0xe1, 0xdd);
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/*
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* Disable the firewire stuff, which apparently steps on IO 0+ on
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* reset. Doh!
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*/
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_6305), 0);
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if (dev != PCI_DEV_INVALID) {
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pci_write_config8(dev, 0x15, 0x1c);
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}
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enable_vt8235_serial();
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uart_init();
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console_init();
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enable_smbus();
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print_spew("In auto.c:main()\r\n");
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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// init_timer();
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outb(5, 0x80);
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print_debug(" Enabling mainboard devices\r\n");
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enable_mainboard_devices();
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print_debug(" Enabling shadow ram\r\n");
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enable_shadow_ram();
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ddr_ram_setup((const struct mem_controller *)0);
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/* Check all of memory */
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#if 0
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if TOTAL_CPUS > 1
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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};
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int i;
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for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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#endif
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if (bist == 0) {
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print_debug(" Doing MTRR init.\r\n");
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early_mtrr_init();
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}
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//dump_pci_devices();
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print_spew("Leaving auto.c:main()\r\n");
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}
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