coreboot-kgpe-d16/src
Arthur Heymans 0f34054964 Makefile.inc: Move adding mcu FIT entries
This can be done using in the INTERMEDIATE target in the proper place.

Change-Id: I28a7764205e0510be89c131058ec56861a479699
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46453
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27 09:18:20 +00:00
..
acpi ACPI: Define acpi_get_preferred_pm_profile() 2020-11-19 22:58:41 +00:00
arch arch/x86/smbios: Update SMBIOS type 16 error correction type 2020-11-25 09:18:04 +00:00
commonlib cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
console
cpu Makefile.inc: Move adding mcu FIT entries 2020-11-27 09:18:20 +00:00
device device: Drop unused HyperTransport code 2020-11-25 09:11:46 +00:00
drivers drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfig 2020-11-26 21:57:44 +00:00
ec ec/google/chromeec: Add more wrappers for regulator control 2020-11-18 06:13:12 +00:00
include arch/x86/smbios: Update SMBIOS type 16 error correction type 2020-11-25 09:18:04 +00:00
lib cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
mainboard mb/google/dedede: Create galtic variant 2020-11-25 21:29:46 +00:00
northbridge nb/amd: Deduplicate nb_common.h 2020-11-25 09:11:58 +00:00
security cbfs: Add metadata cache 2020-11-21 10:43:53 +00:00
soc soc/intel/jasperlake: Enable VT-d and generate DMAR Table 2020-11-27 05:10:12 +00:00
southbridge sb/intel/lynxpoint: Replace hard-coded IDs with defines 2020-11-24 18:37:58 +00:00
superio superio/smsc/sio1036: Support 16-bit IO port addressing 2020-11-18 13:12:11 +00:00
vendorcode vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1483_11 2020-11-26 18:10:47 +00:00
Kconfig