coreboot-kgpe-d16/payloads
Martin Roth 4d7d25f38a payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
Add the option to coreboot to set the SeaBIOS buffers below 0xC0000.
This is a requirement on the Intel Rangeley processor
because it is designed so that only the processor can write
the higher memory areas.  This prevents USB and SATA from bus-mastering
into the buffers when they're set in the typical 0xE0000 area.

This will be set to Y unless defaulted to N by the mainboard or
chipset.

Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak

Change-Id: I15638605d1c66a2277d4b852796db89978551a34
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-12 23:16:29 +02:00
..
bayou GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« 2013-03-01 10:16:08 +01:00
coreinfo payloads/coreinfo/multiboot_module.c: Trivial fix indents 2014-05-23 09:50:21 +02:00
external payloads/external/SeaBIOS: Allow setting buffers below 0xC0000 2014-09-12 23:16:29 +02:00
libpayload arm: Remove some pointless CFLAGS 2014-09-12 22:09:10 +02:00
nvramcui nvramcui: Trim values when setting. 2014-01-19 15:09:29 +01:00
tianocoreboot ARM: Generalize armv7 as arm. 2014-09-08 18:59:23 +02:00