08135332dd
Add platform cpu info for known microcode, print cpuid & processor branding string. This will print as in the following example: CPU: Intel(R) Xeon(R) Platinum 8468H CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130 CPU: AES supported, TXT supported, VT supported Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <bootblock_common.h>
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#include <device/pci.h>
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#include <FsptUpd.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/tco.h>
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#include <soc/iomap.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <intelblocks/lpc_lib.h>
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#include <security/intel/cbnt/cbnt.h>
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#include <soc/pci_devs.h>
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#include <soc/bootblock.h>
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#include <fsp/util.h>
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const FSPT_UPD temp_ram_init_params = {
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.FspUpdHeader = {
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.Signature = FSPT_UPD_SIGNATURE,
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.Revision = 1,
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.Reserved = {0},
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},
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.FsptCoreUpd = {
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.MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
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.MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
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.CodeRegionBase = (UINT32)CACHE_ROM_BASE,
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.CodeRegionLength = (UINT32)CACHE_ROM_SIZE,
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.Reserved1 = {0},
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},
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.FsptConfig = {
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.FsptPort80RouteDisable = 0,
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.ReservedTempRamInitUpd = {0},
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},
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.UnusedUpdSpace0 = {0},
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.UpdTerminator = 0x55AA,
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};
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static uint64_t assembly_timestamp;
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static uint64_t bootblock_timestamp;
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asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
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{
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/*
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* FSP-T does not respect its own API and trashes registers
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* coreboot uses to store its initial timestamp.
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*/
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assembly_timestamp = base_timestamp;
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bootblock_timestamp = timestamp_get();
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fast_spi_cache_bios_region();
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bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp));
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}
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void bootblock_soc_early_init(void)
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{
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fast_spi_early_init(SPI_BASE_ADDRESS);
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pch_enable_lpc();
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/* Set up P2SB BAR. This is needed for PCR to work */
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uint8_t p2sb_cmd = pci_s_read_config8(PCH_DEV_P2SB, PCI_COMMAND);
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pci_s_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY);
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pci_s_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS);
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}
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void bootblock_soc_init(void)
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{
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if (assembly_timestamp > bootblock_timestamp)
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printk(BIOS_WARNING, "Invalid initial timestamp detected\n");
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if (CONFIG(FSP_CAR))
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report_fspt_output();
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if (CONFIG(INTEL_CBNT_LOGGING))
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intel_cbnt_log_registers();
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bootblock_pch_init();
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/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
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tco_configure();
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report_platform_info();
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}
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