coreboot-kgpe-d16/src/soc/intel/xeon_sp
Subrata Banik d19ebe0bd5 soc/intel: Rename pcr.asl to pch_pcr.asl
The PCR (Private Configuration Register) is applicable to access the
P2SB register space starting with the Intel SkyLake generation of SoC.

Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside
the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in
SoC die (same as PCH die for U/H SoC) and another in IOE die.

This patch renames pcr.asl to pch_pcr.asl to reflect the actual source
of the P2SB IP in the die (i.e., SoC die or PCH die).

BUG=b:290856936
TEST=Able to build and boot google/rex.

Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-13 16:37:56 +00:00
..
acpi soc/intel: Rename pcr.asl to pch_pcr.asl 2023-07-13 16:37:56 +00:00
cpx soc/intel: Add max memory speed into dimm info 2023-06-15 15:08:12 +00:00
ebg soc/intel/xeon_sp: Add PM definition for SPR-SP 2023-03-07 22:14:35 +00:00
include/soc soc/intel/xeon_sp: Don't sort struct device cpus for numa 2023-04-14 10:50:44 +00:00
lbg soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bits 2023-06-15 14:14:05 +00:00
ras soc/intel/xeon_sp: Fix HEST table length 2023-06-14 09:53:57 +00:00
skx sb,soc/amd,intel: Sync FADT entries visually 2023-05-10 21:26:55 +00:00
spr soc/intel/xeon_sp/spr: Fix upd_display.c build error 2023-07-07 13:56:02 +00:00
acpi.c
bootblock.c soc/intel/xeon_sp: Report platform cpu info 2023-03-23 21:21:09 +00:00
chip_common.c console: Add format-checking __printf() to die() 2023-05-17 11:23:59 +00:00
finalize.c commonlib/console/post_code.h: Change post code prefix to POSTCODE 2023-06-23 15:06:04 +00:00
Kconfig
lockdown.c soc/intel/xeon_sp: move PCH specific code into lbg directory 2023-02-17 12:34:27 +00:00
lpc.c
Makefile.inc soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP support 2023-03-25 16:33:36 +00:00
memmap.c
pch.c
pmc.c soc/intel/xeon_sp: move PCH specific code into lbg directory 2023-02-17 12:34:27 +00:00
pmutil.c
ramstage.c
report_platform.c soc/intel/xeon_sp: Report platform cpu info 2023-03-23 21:21:09 +00:00
reset.c
romstage.c soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handling 2023-03-22 12:05:47 +00:00
smihandler.c soc/intel/xeon_sp/smihandler.c: enable support for spr-sp 2023-03-24 16:07:23 +00:00
smmrelocate.c
spi.c
uncore.c soc/intel/xeon_sp: Fix very small total memory when CXL is enabled 2023-04-13 07:56:23 +00:00
uncore_acpi.c soc/intel/xeon_sp: Clear reserved field in SRAT 2023-07-11 13:17:02 +00:00
uncore_acpi_cxl.c soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP support 2023-03-25 16:33:36 +00:00
util.c soc/intel/xeon_sp: Don't sort struct device cpus for numa 2023-04-14 10:50:44 +00:00