Vaibhav Shankar 66dbb0c5d6 src/soc/intel/cannonlake: Update C-state latency control limits ... PC10 is a necessary condition for S0ix entry. With the current C-state limits, CPU fails to enter PC10 during S0ix. C-state Latency control limits have to be tuned to new values for PC10 entry. Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/23220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-01-23 05:43:10 +00:00
..
apollolake	soc/intel/common: Add option to pass SoC IO resource	2018-01-17 17:47:33 +00:00
baytrail	security/tpm: Change TPM naming for different layers.	2018-01-18 01:45:35 +00:00
braswell	security/tpm: Change TPM naming for different layers.	2018-01-18 01:45:35 +00:00
broadwell	security/tpm: Change TPM naming for different layers.	2018-01-18 01:45:35 +00:00
cannonlake	src/soc/intel/cannonlake: Update C-state latency control limits	2018-01-23 05:43:10 +00:00
common	security/tpm: Change TPM naming for different layers.	2018-01-18 01:45:35 +00:00
denverton_ns	soc/intel/denverton_ns: Add Denverton-AD system agent id	2017-12-20 16:40:53 +00:00
fsp_baytrail	soc/intel/fsp_baytrail: remove nvm headers and code	2017-12-17 18:29:08 +00:00
fsp_broadwell_de	Constify struct cpu_device_id instances	2017-11-23 05:00:17 +00:00
quark	soc/intel/quark/spi: Correct conversion specifier	2017-11-03 15:22:06 +00:00
skylake	soc/intel/common: Add option to pass SoC IO resource	2018-01-17 17:47:33 +00:00
Kconfig	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00