Nico Huber d23ee5de22 mainboard: Clean up boot_option/reboot_bits in cmos.layout ... Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2016-08-17 00:27:42 +02:00
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acpi	iwave/IWRainBowG6: Fix IASL warning and remark	2015-11-24 22:38:24 +01:00
acpi_tables.c	intel/sch: Merge northbridge and southbridge in src/soc	2016-05-17 21:38:17 +02:00
board_info.txt
cmos.layout	mainboard: Clean up boot_option/reboot_bits in cmos.layout	2016-08-17 00:27:42 +02:00
cstates.c
devicetree.cb	intel/sch: Merge northbridge and southbridge in src/soc	2016-05-17 21:38:17 +02:00
dsdt.asl	intel/sch: Merge northbridge and southbridge in src/soc	2016-05-17 21:38:17 +02:00
fadt.c
hda_verb.c
irq_tables.c
Kconfig	intel/sch: Merge northbridge and southbridge in src/soc	2016-05-17 21:38:17 +02:00
Kconfig.name
Makefile.inc
mptable.c
romstage.c	intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP	2016-06-21 00:43:20 +02:00