coreboot-kgpe-d16

History

Myles Watson d27c08c289 Remove drivers/pci/onboard. The only purpose was for option ROMs, which are now handled more generically using CBFS. Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2009-11-06 23:42:26 +00:00
..
apc_auto.c	Split the two usages of __ROMCC__:	2009-11-06 17:02:51 +00:00
cache_as_ram_auto.c	Split the two usages of __ROMCC__:	2009-11-06 17:02:51 +00:00
chip.h
cmos.layout
Config.lb	Remove drivers/pci/onboard. The only purpose was for option ROMs, which are	2009-11-06 23:42:26 +00:00
devicetree.cb	Remove drivers/pci/onboard. The only purpose was for option ROMs, which are	2009-11-06 23:42:26 +00:00
get_bus_conf.c
irq_tables.c
Kconfig	Define some variables that were not defined. There are a couple left.	2009-10-26 15:14:07 +00:00
mainboard.c
Makefile.inc	Add CONFIG_GENERATE_* for tables so that the user can select which tables not	2009-10-15 13:35:47 +00:00
mb_sysconf.h
mptable.c
Options.lb	Define some variables that were not defined. There are a couple left.	2009-10-26 15:14:07 +00:00
README
resourcemap.c	Define some variables that were not defined. There are a couple left.	2009-10-26 15:14:07 +00:00
spd_addr.h

README


There are a number of outstanding issues:

* we don't have the mc_patch_01000086.h CPU ucode file yet which is
referenced in a comment in src/mainboard/supermicro/h8dmr_fam10/Options.lb.
AMD has not released it yet. This is not a problem specific to this port.

* I'm seeing toolchain issues. I can't get this tree to compile correctly with
gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the
CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness
disappears. This is probably not a problem related to this port specifically.

* setting CONFIG_DEFAULT_CONSOLE_LOGLEVEL lower than 8 simply hangs the boot
shortly after the warm reset triggered by the MCP55 code. I think this too
might be a toolchain problem (but I see it on gcc 3.4 as well as 4.3).

* during startup, the CPU cores talk through each other on serial for a
while. Again, not an issue specific to this port.

* to avoid very slow LZMA decompression I use this port with LZMA compression
disabled in CBFS. I'm not sure what's causing this particular slowness.

See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html

Ward, 2009-09-22

mansoor@iwavesystems.com said, about the last issue:

  Try enabling CONFIG_XIP_ROM_BASE.  It solved the same problem for me in my board.

So, that's a todo.