2063197a4f
src/arch/i386/Makefile.inc For that to work, I had to: - Add a CONFIG_ROMCC variable - Set that variable on all ROMCC boards - conditionally choose romcc or gcc rule based on that variable - remove those two rules from all the boards' Makefiles - switch a couple of boards to HAVE_OPTION_TABLE, as they actually have. Also remove the duplication of rules with the sole difference of if they depend on option_table.h or not. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
55 lines
1.8 KiB
Makefile
55 lines
1.8 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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##
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## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
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##
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driver-y += mainboard.o
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driver-y += m3885.o
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driver-y += ec.o
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driver-y += rtl8168.o
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obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
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obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
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obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
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obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
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obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o
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smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
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# This is part of the conversion to init-obj and away from included code.
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initobj-y += crt0.o
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# FIXME in $(top)/Makefile
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crt0s := $(src)/cpu/x86/16bit/entry16.inc
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crt0s += $(src)/cpu/x86/32bit/entry32.inc
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crt0s += $(src)/cpu/x86/16bit/reset16.inc
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crt0s += $(src)/arch/i386/lib/id.inc
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crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
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ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscripts += $(src)/cpu/x86/16bit/entry16.lds
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ldscripts += $(src)/cpu/x86/16bit/reset16.lds
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ldscripts += $(src)/arch/i386/lib/id.lds
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ldscripts += $(src)/arch/i386/lib/failover.lds
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