coreboot-kgpe-d16/src
Andrey Petrov d39c68a0c0 soc/intel/cannonlake: Add UART initialization
Cannonlake has built-in UART driver as part of LPSS block. However port
mapped decoders are in use as well.

Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29 14:59:32 +00:00
..
acpi
arch arch/x86: update assembly to ensure 16-byte alignment into C 2017-06-29 14:58:59 +00:00
commonlib commonlib/storage: Zero extend MMC capacity 2017-06-27 21:55:49 +00:00
console src/console: add IS_ENABLED() around Kconfig symbol references 2017-06-12 04:08:55 +02:00
cpu cpu/intel: add IS_ENABLED() around Kconfig symbol references 2017-06-28 17:48:42 +00:00
device src/device: add IS_ENABLED() around Kconfig symbol references 2017-06-28 17:48:57 +00:00
drivers drivers/spi: Don't disable non-existent warnings on clang 2017-06-27 17:00:55 +00:00
ec src/ec: add IS_ENABLED() around Kconfig symbol references 2017-06-28 17:49:22 +00:00
include amd/family15h: Add defines for boost and P-state 2017-06-28 18:24:07 +00:00
lib lib/coreboot_tables: Zero framebuffer structure 2017-06-27 02:16:03 +00:00
mainboard mb/siemens/mc_bdx1: Set bus master bit for on-board PCI devices 2017-06-29 14:42:05 +00:00
northbridge nb/haswell: set ASLB gnvs to OpRegion ACPI memory address 2017-06-29 14:40:49 +00:00
soc soc/intel/cannonlake: Add UART initialization 2017-06-29 14:59:32 +00:00
southbridge sis/sis966: Clean up sata.c 2017-06-27 23:50:59 +00:00
superio device/pnp: remove struct io_info 2017-06-13 15:21:58 +02:00
vboot vboot: Separate board name and version number in FWID with a dot 2017-04-29 01:44:10 +02:00
vendorcode vendorcode/amd: Unify Porting.h across all targets 2017-06-27 17:35:39 +00:00
Kconfig Add support for Undefined Behavior Sanitizer 2017-06-14 19:56:59 +02:00