b3f8090f4e
- HAVE_HIGH_TABLES - HAVE_LOW_TABLES - FALLBACK_SIZE Jens Rottmann sent an almost identical patch at the same time, so Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
36 lines
1.2 KiB
Text
36 lines
1.2 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config NORTHBRIDGE_INTEL_I440BX
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bool
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select HAVE_DEBUG_RAM_SETUP
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config SDRAMPWR_4DIMM
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bool
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depends on NORTHBRIDGE_INTEL_I440BX
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default n
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help
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This option affects how the SDRAMC register is programmed.
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Memory clock signals will not be routed properly if this option
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is set wrong.
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If your board has 4 DIMM slots, you must use select this option, in
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your Kconfig file of the board. On boards with 3 DIMM slots,
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do _not_ select this option.
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