75d8d8da47
Add two GPIO macros: 1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the APIC with input assuming the events are edge triggered. 2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose input to SCI assuming the events are level triggered. Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> |
||
---|---|---|
.. | ||
broadcom/cygnus | ||
dmp/vortex86ex | ||
imgtec/pistachio | ||
intel | ||
lowrisc/lowrisc | ||
marvell | ||
mediatek/mt8173 | ||
nvidia | ||
qualcomm | ||
rdc/r8610 | ||
rockchip | ||
samsung | ||
ucb/riscv |