96195eeb71
This patch aligns tegra132 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Rush_Ryu. Change-Id: I5cdf4008a65db84f15c937ef53aab5e4d3ef24c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5c5c63d7b6399d3eb8a211b15d47829fe93a591 Original-Change-Id: Ifafd4d42d4fb04a1c37e8a5f23877c2b550cf44c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224505 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9369 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
108 lines
2.9 KiB
C
108 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2014, NVIDIA CORPORATION.
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/clk_rst.h>
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#include <soc/clock.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/padconfig.h>
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#include <soc/power.h>
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#define I2C6_BUS 5
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#define I2C6_PADCTL 0xC001
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#define DPAUX_HYBRID_PADCTL 0x545C0124
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static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE;
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static int partition_clamp_on(int id)
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{
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return read32(&pmc->clamp_status) & (1 << id);
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}
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static void remove_clamps(int id)
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{
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if (!partition_clamp_on(id))
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return;
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/* Remove clamp */
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write32((1 << id), &pmc->remove_clamping_cmd);
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/* Wait for clamp off */
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while (partition_clamp_on(id))
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;
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}
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static void enable_sor_periph_clocks(void)
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{
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clock_enable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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}
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static void disable_sor_periph_clocks(void)
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{
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clock_disable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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}
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static void unreset_sor_periphs(void)
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{
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clock_clr_reset(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX);
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}
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void soc_configure_i2c6pad(void)
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{
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/*
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* I2C6 on Tegra124/132 requires some special init.
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* The SOR block must be unpowergated, and a couple of
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* display-based peripherals must be clocked and taken
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* out of reset so that a DPAUX register can be
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* configured to enable the I2C6 mux routing.
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* Afterwards, we can disable clocks to the display blocks
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* and put Host1X back in reset. DPAUX must remain out of
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* reset and the SOR partition must remained unpowergated.
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*/
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power_ungate_partition(POWER_PARTID_SOR);
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/* Host1X needs a valid clock source so DPAUX can be accessed */
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clock_configure_source(host1x, PLLP, 204000);
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enable_sor_periph_clocks();
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remove_clamps(POWER_PARTID_SOR);
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unreset_sor_periphs();
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/* Now we can write the I2C6 mux in DPAUX */
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write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
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/*
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* Delay before turning off Host1X/DPAUX clocks.
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* This delay is needed to keep the sequence from
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* hanging the system.
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*/
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udelay(CLOCK_PLL_STABLE_DELAY_US);
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/* Stop Host1X/DPAUX clocks and reset Host1X */
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disable_sor_periph_clocks();
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clock_set_reset_l(CLK_L_HOST1X);
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}
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