3708cb56cb
To control I2S in MT8195 for dojo project, we need to enable adsp power before audio power. Therefore, we need to update bus protection steps to correct the setting. TEST=build pass BUG=b:204391159 BRANCH=cherry Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: I0bcf1ddeebf0d3df0a1d6b22273123be1aaf85a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63106 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <soc/infracfg.h>
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#include <soc/mtcmos.h>
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enum {
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VPPSYS0_PROT_STEP_6_MASK = 0x00100000,
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VPPSYS0_PROT_STEP_5_MASK = 0x0007F8FF,
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VPPSYS0_PROT_STEP_4_MASK = 0x00800000,
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VPPSYS0_PROT_STEP_3_MASK = 0x01600300,
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VPPSYS0_PROT_STEP_2_MASK = 0x80381DC7,
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VPPSYS0_PROT_STEP_1_MASK = 0x00000400,
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VDOSYS0_PROT_STEP_5_MASK = 0x00200000,
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VDOSYS0_PROT_STEP_4_MASK = 0x3FC00000,
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VDOSYS0_PROT_STEP_3_MASK = 0x00000040,
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VDOSYS0_PROT_STEP_2_MASK = 0x00800000,
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VDOSYS0_PROT_STEP_1_MASK = 0x403E6238,
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VPPSYS1_PROT_STEP_3_MASK = 0x000400C0,
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VPPSYS1_PROT_STEP_2_MASK = 0x00800000,
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VPPSYS1_PROT_STEP_1_MASK = 0x000001E0,
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VDOSYS1_PROT_STEP_3_MASK = 0x00000400,
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VDOSYS1_PROT_STEP_2_MASK = 0x00400000,
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VDOSYS1_PROT_STEP_1_MASK = 0xC0000000,
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ADSP_PROT_STEP_1_MASK = 0x0001D000,
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AUDIO_PROT_STEP_1_MASK = 0x00000A00,
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};
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void mtcmos_protect_display_bus(void)
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{
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr,
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VPPSYS0_PROT_STEP_6_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
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VPPSYS0_PROT_STEP_5_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr,
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VPPSYS0_PROT_STEP_4_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
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VPPSYS0_PROT_STEP_3_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
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VPPSYS0_PROT_STEP_2_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr,
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VPPSYS0_PROT_STEP_1_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr,
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VDOSYS0_PROT_STEP_5_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
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VDOSYS0_PROT_STEP_4_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr,
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VDOSYS0_PROT_STEP_3_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
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VDOSYS0_PROT_STEP_2_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
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VDOSYS0_PROT_STEP_1_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
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VPPSYS1_PROT_STEP_3_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
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VPPSYS1_PROT_STEP_2_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
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VPPSYS1_PROT_STEP_1_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr_2,
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VDOSYS1_PROT_STEP_3_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
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VDOSYS1_PROT_STEP_2_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_mm_clr,
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VDOSYS1_PROT_STEP_1_MASK);
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}
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void mtcmos_protect_audio_bus(void)
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{
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr_2,
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ADSP_PROT_STEP_1_MASK);
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write32(&mt8195_infracfg_ao->infra_topaxi_protecten_clr_2,
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AUDIO_PROT_STEP_1_MASK);
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}
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