d64d426b4f
This change adds a helper function `pcie_rp_enable_mask()` that returns a 32-bit mask indicating the status (enabled/disabled) of PCIe root ports (in the groups table) as configured by the mainboard in the device tree. With this helper function, SoC chip config does not need to add another `PcieRpEnable[]` config to identify what root ports are enabled. Change-Id: I7ce5fca1c662064fd21f0961dac13cda1fa2ca44 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48968 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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alderlake | ||
apollolake | ||
baytrail | ||
braswell | ||
broadwell | ||
cannonlake | ||
common | ||
denverton_ns | ||
elkhartlake | ||
icelake | ||
jasperlake | ||
quark | ||
skylake | ||
tigerlake | ||
xeon_sp | ||
Kconfig |