Lee Leahy d75ed0bfd9 soc/intel/quark: Disable the ROM shadow ... Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing successful display of 0x000ffff0 - 0x000fffff does not match the end of the SPI flash. Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>		2016-03-21 19:46:59 +01:00
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include/soc	soc/intel/quark: Disable the ROM shadow	2016-03-21 19:46:59 +01:00
romstage	soc/intel/quark: Disable the ROM shadow	2016-03-21 19:46:59 +01:00
acpi.c	soc/intel/quark: Initialize some of the FADT base registers	2016-02-29 04:59:56 +01:00
chip.c	soc/intel/quark: Add the UPD support for SiliconInit	2016-03-08 16:40:40 +01:00
chip.h	soc/intel/quark: Set the UPD values for MemoryInit	2016-03-08 18:06:12 +01:00
Kconfig	soc/intel/quark: Call FSP SiliconInit	2016-02-10 03:12:10 +01:00
Makefile.inc	soc/intel/quark: Initialize some of the FADT base registers	2016-02-29 04:59:56 +01:00
memmap.c	soc/intel/quark: Enable ESRAM	2016-02-08 20:15:05 +01:00
northcluster.c	soc/intel/quark: Reserve non-MMIO space	2016-02-29 05:00:27 +01:00
pmc.c	soc/intel/quark: Initialize some of the FADT base registers	2016-02-29 04:59:56 +01:00
tsc_freq.c	soc/intel/quark: Enable Serial Port	2016-02-09 16:20:38 +01:00
uart.c	soc/intel/quark: Use single ID value for HSUART1	2016-02-19 20:24:22 +01:00
uart_common.c	soc/intel/quark: Enable HSUART1	2016-02-18 20:36:53 +01:00