Kane Chen d779605c29 soc/intel/apollolake: Properly disable PCIe root ports ... 1. The hotplug feature needs to be disabled so that pcie root ports will be disabled by fsp 2. Correct PcieRootPortEn mapping. The correct mapping should be like below PcieRootPortEn[0] ==> 00:14.0 PcieRootPortEn[1] ==> 00:14.1 PcieRootPortEn[2] ==> 00:13.0 PcieRootPortEn[3] ==> 00:13.1 PcieRootPortEn[4] ==> 00:13.2 PcieRootPortEn[5] ==> 00:13.3 BUG=chrome-os-partner:54288 BRANCH=None TEST=Checked pcie root port is disabled properly and make sure pcie ports are coalesced. Also make sure the device will still be enabled after coalescence when pcie on function 0 is disabled devicetree Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/15595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-07-15 18:20:54 +02:00
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broadcom/cygnus	soc/*: fix uart's regwidth specification in cbtables	2016-02-21 12:26:05 +01:00
dmp/vortex86ex	dmp/vortex86ex: Merge northbridge and southbridge into soc	2016-05-05 20:06:33 +02:00
imgtec/pistachio	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
intel	soc/intel/apollolake: Properly disable PCIe root ports	2016-07-15 18:20:54 +02:00
marvell	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
mediatek/mt8173	soc: Remove newline from CHIP_NAME	2016-07-07 17:14:01 +02:00
nvidia	Documentation: Fix doxygen errors	2016-07-12 22:41:02 +02:00
qualcomm	Documentation: Fix doxygen errors	2016-07-12 22:41:02 +02:00
rdc/r8610	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
rockchip	rockchip/rk3399: extend romstage range	2016-07-15 00:38:15 +02:00
samsung	Documentation: Fix doxygen errors	2016-07-12 22:41:02 +02:00
ucb/riscv	arch/riscv: Move CBMEM into RAM	2016-07-15 03:01:02 +02:00