d8bc5c127a
We only want to return an ACPI name for a USB port if the controller physically has the port. This has the desired side effect of making the usb_acpi driver skip generating an ACPI node for a device which has no port. This prevents writing an invalid SSDT table which the OS then complains about. BUG=b:154756391, b:158096224 TEST=Boot picasso trembyle and verify HS05, HS06 and SS05 are no longer generated. Also checked the logs and saw the devices being ignored. \_SB.PCI0.LPCB.EC0.CREC.TUN0: Cros EC I2C Tunnel at GENERIC: 0.0 \_SB.PCI0.LPCB.EC0.CREC.MSTH: Cros EC I2C Tunnel at GENERIC: 1.0 \_SB.PCI0.LPCB.EC0.CREC.ECA0: Cros EC audio codec at GENERIC: 0.0 \_SB.PCI0.PBRA.XHC0.RHUB.HS01: Left Type-C Port at USB2 port 0 \_SB.PCI0.PBRA.XHC0.RHUB.HS02: Left Type-A Port at USB2 port 1 \_SB.PCI0.PBRA.XHC0.RHUB.HS03: Right Type-A Port at USB2 port 2 \_SB.PCI0.PBRA.XHC0.RHUB.HS04: Right Type-C Port at USB2 port 3 xhci_acpi_name: USB2 port 4 does not exist on xHC PCI: 03:00.3 xhci_acpi_name: USB2 port 5 does not exist on xHC PCI: 03:00.3 \_SB.PCI0.PBRA.XHC0.RHUB.SS01: Left Type-C Port at USB3 port 0 \_SB.PCI0.PBRA.XHC0.RHUB.SS02: Left Type-A Port at USB3 port 1 \_SB.PCI0.PBRA.XHC0.RHUB.SS03: Right Type-A Port at USB3 port 2 \_SB.PCI0.PBRA.XHC0.RHUB.SS04: Right Type-C Port at USB3 port 3 xhci_acpi_name: USB3 port 4 does not exist on xHC PCI: 03:00.3 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia645380bea74f39fd94e2f9cbca3fcd4d18a878e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43354 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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|---|---|---|
| 3rdparty | ||
| Documentation | ||
| LICENSES | ||
| configs | ||
| payloads | ||
| src | ||
| tests | ||
| util | ||
| .checkpatch.conf | ||
| .clang-format | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| AUTHORS | ||
| COPYING | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.inc | ||
| README.md | ||
| gnat.adc | ||
| toolchain.inc | ||
README.md
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
Build Requirements
- make
- gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case). - iasl (for targets with ACPI support)
- pkg-config
- libssl-dev (openssl)
Optional:
- doxygen (for generating/viewing documentation)
- gdb (for better debugging facilities on some targets)
- ncurses (for
make menuconfigandmake nconfig) - flex and bison (for regenerating parsers)
Building coreboot
Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
Copyright and License
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.