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Duncan Laurie d9af3cecae device: Add an ACPI device name and path concept to devices 
Add a function to "struct device_operations" to return the ACPI name
for the device, and helper functions to find this name (either from
the device or its parent) and to build a fully qualified ACPI path
from the root device.

This addition will allow device drivers to generate their ACPI AML in
the SSDT at boot, with customization supplied by devicetree.cb,
instead of needing custom DSDT ASL for every mainboard.

The root device acpi_name is defined as "\\_SB" and is used to start
the path when building a fully qualified name.

This requires SOC support to provide handlers for returning the ACPI
name for devices that it owns, and those names must match the objects
declared in the DSDT.  The handler can be done either in each device
driver or with a global handler for the entire SOC.

Simplified example of how this can be used for an i2c device declared
in devicetree.cb with:

  chip soc/intel/skylake          # "\_SB" (from root device)
    device domain 0 on            # "PCI0"
      device pci 19.2 on          # "I2C4"
        chip drivers/i2c/test0
          device i2c 1a.0 on end  # "TST0"
        end
      end
    end
  end

And basic SSDT generating code in the device driver:

  acpigen_write_scope(acpi_device_scope(dev));
  acpigen_write_device(acpi_device_name(dev));
  acpigen_write_string("_HID", "TEST0000");
  acpigen_write_byte("_UID", 0);
  acpigen_pop_len(); /* device */
  acpigen_pop_len(); /* scope */

Will produce this ACPI code:

  Scope (\_SB.PCI0.I2C4) {
    Device (TST0) {
      Name (_HID, "TEST0000")
      Name (_UID, 0)
    }
  }

Change-Id: Ie149595aeab96266fa5f006e7934339f0119ac54
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14840
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 		2016-05-21 05:59:52 +02:00
3rdparty 3rdparty/blobs: add more Qualcomm stubs 2016-05-10 21:22:28 +02:00
Documentation Documentation/Intel: Update the documentation 2016-05-18 19:47:16 +02:00
payloads libpayload: cbfs: Add cbfs_handle API for more fine-grained accesses 2016-05-17 22:48:28 +02:00
src device: Add an ACPI device name and path concept to devices 2016-05-21 05:59:52 +02:00
util util/cbfstool: allow option to honor FSP modules' linked address 2016-05-18 03:19:12 +02:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore .gitignore: add build and libpayload dirs for nvramcui payload 2016-05-03 04:16:45 +02:00
.gitmodules git modules: rename git submodules to avoid hierarchies 2016-02-11 20:55:55 +01:00
.gitreview
…
COPYING
…
MAINTAINERS MAINTAINERS: Add maintainer for Pineview & x4x chipsets & boards 2016-04-19 19:25:59 +02:00
Makefile Makefile: Update payload clean targets 2016-03-09 17:01:56 +01:00
Makefile.inc jenkins: Run the romcc test suite 2016-05-19 00:14:15 +02:00
README
…
toolchain.inc toolchain.inc: test IASL by version string instead of number 2016-03-04 16:36:25 +01:00

README 

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.