Scott Duplichan daecb1888e According to AMD documentation, cache type WP should be used for ... execution from flash memory. Coreboot uses WB. While there is no noticeable performance difference between the two settings, use of WB can cause a problem for a jtag debugger. The attached patch changes AMD cache as ram setting for flash execution from WB to WP. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2011-02-10 20:49:56 +00:00
..
cache_as_ram.inc	According to AMD documentation, cache type WP should be used for	2011-02-10 20:49:56 +00:00
disable_cache_as_ram.c	Following patch reworks car_disable into C. Tested, works here. I compared	2010-05-16 21:51:34 +00:00
post_cache_as_ram.c	1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c	2010-11-22 22:00:52 +00:00