coreboot-kgpe-d16/src/soc/intel/broadwell/acpi
Duncan Laurie cf544ac1f9 broadwell: Remove XHCI workarounds on WPT
The workarounds in ACPI methods for D0/D3 transition that are
used on haswell/LPT do not all apply to broadwell/WPT.

BUG=chrome-os-partner:28234
BRANCH=broadwell
TEST=build and boot on samus, test USB functionality and wake
and ensure the device still does into D3 state

Change-Id: Ic3a75f5bf50e826ade7d942b48cfebb75cf976e6
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 1b54d105957ee80ca34048c42fb8f241731281cf
Original-Change-Id: I877afd51fc6c9b7906e923b893fc31bdf2cd1090
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240850
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9488
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10 20:13:56 +02:00
..
adsp.asl broadwell: Misc updates from 2.1.0 ref code 2015-03-27 05:39:35 +01:00
cpu.asl acpi: Generate valid ACPI processor objects 2015-02-16 21:02:30 +01:00
ctdp.asl acpi: Generate valid ACPI processor objects 2015-02-16 21:02:30 +01:00
device_nvs.asl
ehci.asl
globalnvs.asl broadwell: Add support for ACPI \_GPE._SWS 2015-04-10 19:22:25 +02:00
gpio.asl
hda.asl
irqlinks.asl intel: Remove IRQ1 from possible PIRQ assignemnt. 2014-11-25 23:47:20 +01:00
lpc.asl
pch.asl broadwell: Change all SoC headers to <soc/headername.h> system 2015-04-07 18:23:23 +02:00
pci_irqs.asl
pcie.asl
pcie_port.asl
platform.asl broadwell: Add support for ACPI \_GPE._SWS 2015-04-10 19:22:25 +02:00
sata.asl
serialio.asl broadwell: Increase I2C SDA hold timing to 300ns 2015-04-10 19:31:33 +02:00
sleepstates.asl
smbus.asl
systemagent.asl broadwell: Change all SoC headers to <soc/headername.h> system 2015-04-07 18:23:23 +02:00
xhci.asl broadwell: Remove XHCI workarounds on WPT 2015-04-10 20:13:56 +02:00