696ebc2dbc
The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but Browell supports up to 4 ports, so we need to support setting IOBP for ports 2 and 3 as well. The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only guessed by looking at ports 0 and 1 and extrapolating from there. Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work so we can assume that port 2 and 3 magic numbers are valid, but having someone confirm them (through non-public documents?) would be great. Change-Id: I59911cfa677749ceea9a544a99b444722392e72d Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18408 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
167 lines
3.7 KiB
C
167 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_INTEL_BROADWELL_CHIP_H_
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#define _SOC_INTEL_BROADWELL_CHIP_H_
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struct soc_intel_broadwell_config {
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/*
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* Interrupt Routing configuration
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* If bit7 is 1, the interrupt is disabled.
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*/
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uint8_t pirqa_routing;
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uint8_t pirqb_routing;
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uint8_t pirqc_routing;
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uint8_t pirqd_routing;
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uint8_t pirqe_routing;
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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/* GPE configuration */
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uint32_t gpe0_en_1;
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uint32_t gpe0_en_2;
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uint32_t gpe0_en_3;
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uint32_t gpe0_en_4;
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/* GPIO SMI configuration */
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uint32_t alt_gp_smi_en;
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/* IDE configuration */
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uint8_t sata_port_map;
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uint32_t sata_port0_gen3_tx;
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uint32_t sata_port1_gen3_tx;
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uint32_t sata_port2_gen3_tx;
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uint32_t sata_port3_gen3_tx;
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uint32_t sata_port0_gen3_dtle;
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uint32_t sata_port1_gen3_dtle;
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uint32_t sata_port2_gen3_dtle;
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uint32_t sata_port3_gen3_dtle;
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/*
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* SATA DEVSLP Mux
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* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
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* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
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*/
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uint8_t sata_devslp_mux;
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/*
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* DEVSLP Disable
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* 0: DEVSLP is enabled
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* 1: DEVSLP is disabled
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*/
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uint8_t sata_devslp_disable;
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* Enable linear PCIe Root Port function numbers starting at zero */
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uint8_t pcie_port_coalesce;
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/* Force root port ASPM configuration with port bitmap */
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uint8_t pcie_port_force_aspm;
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/* Put SerialIO devices into ACPI mode instead of a PCI device */
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uint8_t sio_acpi_mode;
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/* I2C voltage select: 0=3.3V 1=1.8V */
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uint8_t sio_i2c0_voltage;
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uint8_t sio_i2c1_voltage;
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/* Enable ADSP power gating features */
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uint8_t adsp_d3_pg_enable;
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uint8_t adsp_sram_pg_enable;
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/*
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* Clock Disable Map:
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* [21:16] = CLKOUT_PCIE# 5-0
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* [24] = CLKOUT_ITPXDP
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*/
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uint32_t icc_clock_disable;
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/*
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* Digital Port Hotplug Enable:
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* 0x04 = Enabled, 2ms short pulse
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* 0x05 = Enabled, 4.5ms short pulse
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* 0x06 = Enabled, 6ms short pulse
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* 0x07 = Enabled, 100ms short pulse
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*/
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u8 gpu_dp_b_hotplug;
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u8 gpu_dp_c_hotplug;
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u8 gpu_dp_d_hotplug;
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/* Panel power sequence timings */
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u8 gpu_panel_port_select;
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u8 gpu_panel_power_cycle_delay;
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u16 gpu_panel_power_up_delay;
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u16 gpu_panel_power_down_delay;
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u16 gpu_panel_power_backlight_on_delay;
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u16 gpu_panel_power_backlight_off_delay;
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/* Panel backlight settings */
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u32 gpu_cpu_backlight;
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u32 gpu_pch_backlight;
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/*
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* Graphics CD Clock Frequency
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* 0 = 337.5MHz
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* 1 = 450MHz
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* 2 = 540MHz
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* 3 = 675MHz
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*/
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int cdclk;
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/* Enable S0iX support */
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int s0ix_enable;
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/*
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* Minimum voltage for C6/C7 state:
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* 0x67 = 1.6V (full swing)
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* ...
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* 0x79 = 1.7V
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* ...
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* 0x83 = 1.8V (no swing)
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*/
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int vr_cpu_min_vid;
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/*
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* Set slow VR ramp rate on C-state exit:
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* 0 = Fast VR ramp rate / 2
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* 1 = Fast VR ramp rate / 4
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* 2 = Fast VR ramp rate / 8
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* 3 = Fast VR ramp rate / 16
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*/
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int vr_slow_ramp_rate_set;
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/* Enable slow VR ramp rate */
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int vr_slow_ramp_rate_enable;
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/* Deep SX enable */
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int deep_sx_enable_ac;
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int deep_sx_enable_dc;
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/* TCC activation offset */
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int tcc_offset;
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};
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typedef struct soc_intel_broadwell_config config_t;
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extern struct chip_operations soc_ops;
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#endif
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