1ca8b6e3c3
1. Fix typo in *based*
2. Use official spelling for Alder Lake
3. Mention *Converged Security*
4. Capitalize CMOS
Change-Id: I36eac6f017229a3e9261e0eb84371421927e1cae
Fixes: 941239d54d (Documentation/releases: Update 4.16 release notes)
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
27 lines
1 KiB
Markdown
27 lines
1 KiB
Markdown
Upcoming release - coreboot 4.16
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================================
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The 4.16 release is planned for February, 2022.
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We are increasing the frequency of releases in order to enable others to release quarterly on
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a fresher version of coreboot.
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Update this document with changes that should be in the release notes.
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* Please use Markdown.
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* See the past few release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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Significant changes
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-------------------
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### Add significant changes here
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### Option to disable Intel Management Engine
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Disable the Intel (Converged Security) Management Engine ((CS)ME) via HECI based
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on Intel Core processors from Skylake to Alder Lake. State is set based on a
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CMOS value of `me_state`. A value of `0` will result in a (CS)ME state of `0`
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(working) and value of `1` will result in a (CS)ME state of `3` (disabled). For
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an example CMOS layout and more info, see
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[cse.c](../../src/soc/intel/common/block/cse/cse.c).
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