d8214d7e0e
SoCs from Skylake on have many settings as so called private con- figuration registers (PCRs). These are organized as 256 ports with a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's BAR to access them. Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19593 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
||
|---|---|---|
| .. | ||
| Makefile | ||
| ahci.c | ||
| amb.c | ||
| cpu.c | ||
| gfx.c | ||
| gpio.c | ||
| gpio_groups.c | ||
| inteltool.8 | ||
| inteltool.c | ||
| inteltool.h | ||
| ivy_memory.c | ||
| memory.c | ||
| pcie.c | ||
| pcr.c | ||
| pcr.h | ||
| powermgt.c | ||
| rootcmplx.c | ||
| spi.c | ||