Matt DeVillier d77525b5bd vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE ... Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h. Add/correct values for DDR5, LPDDR5, LPDDR5X. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2022-08-24 15:14:15 +00:00
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amd	vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE	2022-08-24 15:14:15 +00:00
cavium	rules.h: Use more consistent naming	2022-05-16 21:52:22 +00:00
eltan	vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependency	2022-02-22 15:56:03 +00:00
google	util/elogtool: Mark redundant boot mode event type as deprecated	2022-08-06 14:06:33 +00:00
intel	vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01	2022-08-07 19:39:43 +00:00
mediatek	mb/google: Replace some strings in regulator.c	2022-07-21 10:30:57 +00:00
siemens
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00