coreboot-kgpe-d16/src/northbridge/intel/x4x
Arthur Heymans df946b8696 nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset
The dram controller cannot fully initialize the dram on warm
reset (receive enable calibration consistently fails) therefore
requiring cached timings.

This option is mostly useful when rebooting after having flashed a new
rom which overwrites the mrc cache region.

Change-Id: I405c0eca076fe081641ede9a670f734c98cbf8fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-17 14:17:31 +00:00
..
acpi
acpi.c nb/x4x: Get rid of device_t 2018-04-30 09:22:32 +00:00
bootblock.c
chip.h
dq_dqs.c nb/intel/x4x: Implement write leveling 2018-05-24 13:03:45 +00:00
early_init.c nb/intel/x4x: Change memory layout to improve MTRR 2018-05-01 17:42:30 +00:00
gma.c nb/intel/x4x: Deprecate native graphic init 2018-06-14 09:40:55 +00:00
iomap.h
Kconfig nb/intel/x4x: Deprecate native graphic init 2018-06-14 09:40:55 +00:00
Makefile.inc nb/intel/x4x: Switch to POSTCAR_STAGE 2018-06-05 07:49:20 +00:00
northbridge.c {mb,nb,soc}: Remove references to pci_bus_default_ops() 2018-05-08 03:01:04 +00:00
ram_calc.c nb/intel/x4x: Switch to POSTCAR_STAGE 2018-06-05 07:49:20 +00:00
raminit.c nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset 2018-06-17 14:17:31 +00:00
raminit_ddr23.c nb/intel/x4x: Fix a few things in set_enhanced_mode 2018-06-14 09:37:50 +00:00
raminit_tables.c nb/intel/x4x: Adapt post JEDEC for DDR3 2018-05-24 13:05:32 +00:00
rcven.c nb/intel/x4x/rcven.c: Change the verbosity of some messages 2018-04-17 10:41:57 +00:00
x4x.h nb/intel/x4x: Add the option for stacked channel map settings 2018-06-14 09:35:30 +00:00