coreboot-kgpe-d16/src
Duncan Laurie dfb373541b google/reef: Enable I2C2 for use in bootblock
Enable I2C bus 2 for early init so it can be used by vboot for TPM
communication for verifying the memory init code.

BUG=chrome-os-partner:53336
BRANCH=none
TEST=build and boot on reef

Change-Id: Id4940ab01d8ccf288ab0a7a9a2f19867ed464e8d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16059
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-06 04:36:13 +02:00
..
acpi src/acpi: Capitalize ACPI and SATA 2016-07-31 19:25:40 +02:00
arch acpi: Generate object for coreboot table region 2016-08-06 04:35:43 +02:00
commonlib cbmem: share additional time stamps IDs 2016-07-20 22:09:24 +02:00
console arch/x86: Enable postcar console 2016-08-01 21:40:23 +02:00
cpu Remove non-ascii & unprintable characters 2016-08-01 21:44:45 +02:00
device src/device: Capitalize CPU, RAM and ROM 2016-07-31 18:33:30 +02:00
drivers drivers/intel/fsp1_1: only set a base address for FSP in COREBOOT CBFS 2016-08-06 04:33:55 +02:00
ec chromeec: Chrome EC firmware source selection for EC and PD firmwares 2016-08-04 17:18:38 +02:00
include elog: Include declarations for boot count functions unconditionally 2016-08-02 18:37:55 +02:00
lib lib/timestamp: Add timestamps to CBMEM in POSTCAR stage 2016-08-04 03:27:08 +02:00
mainboard google/reef: Enable I2C2 for use in bootblock 2016-08-06 04:36:13 +02:00
northbridge amd/amdfam10: eliminate dead code 2016-08-02 14:02:51 +02:00
soc soc/intel/quark: Add missing breaks 2016-08-05 15:36:18 +02:00
southbridge sb/amd/sb700: Do not reset fifo after skipping the sent bytes 2016-08-04 21:47:50 +02:00
superio superio/fintek/f81866d: Add support for UART 3/4 2016-08-02 18:57:36 +02:00
vboot src/vboot: Capitalize RAM and CPU 2016-07-31 19:31:41 +02:00
vendorcode chromeos mainboards: remove chromeos.asl 2016-07-30 01:36:32 +02:00
Kconfig src/Kconfig: Capitalize ROM 2016-07-31 18:34:16 +02:00