6af3e6f4ff
Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. The platform (x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Change-Id: Id3b3b3abbb3920d68d77fd7db996a1dc3c6b85a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25596 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
124 lines
3.1 KiB
C
124 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_def.h>
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#include <pc80/mc146818rtc.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801jx.h"
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#include "nvs.h"
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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*/
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u16 pmbase = DEFAULT_PMBASE;
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u8 smm_initialized = 0;
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/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
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* by coreboot.
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*/
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global_nvs_t *gnvs = (global_nvs_t *)0x0;
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void *tcg = (void *)0x0;
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void *smi1 = (void *)0x0;
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int southbridge_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x32:
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printk(BIOS_DEBUG, "OS Init\n");
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/* gnvs->smif:
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* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*/
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gnvs->smif = 0;
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return 1; /* IO trap handled */
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}
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/* Not handled */
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return 0;
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}
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void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
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{
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gnvs = *(global_nvs_t **)0x500;
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tcg = *(void **)0x504;
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smi1 = *(void **)0x508;
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*smm_done = 1;
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}
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void southbridge_smi_monitor(void)
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{
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#define IOTRAP(x) (trap_sts & (1 << x))
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u32 trap_sts, trap_cycle;
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u32 data, mask = 0;
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int i;
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trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
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RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
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trap_cycle = RCBA32(0x1e10);
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for (i=16; i<20; i++) {
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if (trap_cycle & (1 << i))
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mask |= (0xff << ((i - 16) << 3));
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}
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/* IOTRAP(3) SMI function call */
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if (IOTRAP(3)) {
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if (gnvs && gnvs->smif)
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io_trap_handler(gnvs->smif); // call function smif
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return;
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}
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/* IOTRAP(2) currently unused
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* IOTRAP(1) currently unused */
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/* IOTRAP(0) SMIC */
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if (IOTRAP(0)) {
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if (!(trap_cycle & (1 << 24))) { // It's a write
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printk(BIOS_DEBUG, "SMI1 command\n");
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data = RCBA32(0x1e18);
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data &= mask;
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// if (smi1)
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// southbridge_smi_command(data);
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// return;
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}
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// Fall through to debug
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}
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printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
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for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
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printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
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printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
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printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
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if (!(trap_cycle & (1 << 24))) {
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/* Write Cycle */
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data = RCBA32(0x1e18);
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printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
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}
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#undef IOTRAP
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}
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void southbridge_finalize_all(void)
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{
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}
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