coreboot-kgpe-d16/src/mainboard/iei/pcisa-lx-800-r10
Warren Turkal e0afe735a0 All these boards already had the CACHE_AS_RAM option in their individual
configs. I just moved it the the CPU that they all use.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 21:18:26 +00:00
..
chip.h Remove unused mainboard_config definitions. Trivial. 2010-08-26 18:24:04 +00:00
devicetree.cb Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster" 2010-05-05 13:12:42 +00:00
irq_tables.c Cut the crap. 2010-09-21 21:16:27 +00:00
Kconfig All these boards already had the CACHE_AS_RAM option in their individual 2010-09-27 21:18:26 +00:00
mainboard.c Carl-Daniel's part: 2009-02-18 20:41:57 +00:00
romstage.c This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way. 2010-06-10 15:24:57 +00:00