42315688b5
Needs the ramstage configuration enabling of SuperIO GPIO pnp devices for BSEL straps. Also needs VSBGATE# to be on for ram to be powered during S3. TESTED with 800MHz and 1067MHz FSB CPUs at the correct straps when resuming from S3. Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
149 lines
3.7 KiB
Text
149 lines
3.7 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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## Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/i945
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device cpu_cluster 0 on
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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chip cpu/intel/model_1067x
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device lapic 0xACAC off end
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end
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end
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device domain 0 on
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device pci 00.0 on # host bridge
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subsystemid 0x1458 0x5000
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end
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device pci 01.0 on # i945 PCIe root port
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subsystemid 0x1458 0x5000
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ioapic_irq 2 INTA 0x10
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end
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device pci 02.0 on # vga controller
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subsystemid 0x1458 0xd000
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ioapic_irq 2 INTA 0x10
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end
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x86"
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register "pirqd_routing" = "0x85"
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register "pirqe_routing" = "0x83"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x85"
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register "gpe0_en" = "0"
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register "ide_legacy_combined" = "0x0"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x0"
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register "sata_ahci" = "0x0"
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register "p_cnt_throttling_supported" = "0"
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device pci 1b.0 on # High Definition Audio
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ioapic_irq 2 INTA 0x10
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end
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device pci 1c.0 on end # PCIe
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device pci 1c.1 on end # PCIe
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#device pci 1c.2 off end # PCIe port 3
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#device pci 1c.3 off end # PCIe port 4
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#device pci 1c.4 off end # PCIe port 5
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#device pci 1c.5 off end # PCIe port 6
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device pci 1d.0 on # USB UHCI
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ioapic_irq 2 INTA 0x10
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end
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device pci 1d.1 on # USB UHCI
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ioapic_irq 2 INTB 0x11
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end
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device pci 1d.2 on # USB UHCI
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ioapic_irq 2 INTC 0x12
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end
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device pci 1d.3 on # USB UHCI
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ioapic_irq 2 INTD 0x13
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end
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device pci 1d.7 on # USB2 EHCI
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ioapic_irq 2 INTA 0x10
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end
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # LPC bridge
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ioapic_irq 2 INTA 0x10
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chip superio/winbond/w83627dhg
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # Keyboard
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irq 0x72 = 12 # Mouse
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end
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device pnp 2e.6 off end # SPI
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device pnp 2e.7 on end # GPIO6
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device pnp 2e.8 off end # WDTO# & PLED
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device pnp 2e.9 off end # GPIO2
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device pnp 2e.109 on # GPIO3
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irq 0xf0 = 0xf3 # BSEL straps to output
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irq 0xf2 = 0x08 # INVERT GPIO33
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end
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device pnp 2e.209 on # GPIO4
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irq 0xf5 = 0xf8
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end
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device pnp 2e.309 on # GPIO5
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irq 0xe0 = 0xde
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end
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device pnp 2e.a on # ACPI
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irq 0x70 = 0
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irq 0xe4 = 0x10 # VSBGATE# to power dram during S3
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end
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device pnp 2e.b on # HWM
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io 0x60 = 0x290
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irq 0x70 = 0
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end
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device pnp 2e.c on end # PECI, SST
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end
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end
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device pci 1f.1 on # IDE
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ioapic_irq 2 INTB 0x11
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end
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device pci 1f.2 on # SATA
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ioapic_irq 2 INTC 0x12
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end
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device pci 1f.3 on # SMBus
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ioapic_irq 2 INTD 0x13
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end
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end
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end
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end
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