Srinidhi N Kaushik eab9290b5f vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake ... Update FSP headers for Tiger Lake platform generated based on FSP version 4133 to include post PRQ UPDs. BUG=b:188452018 BRANCH=none TEST=build voxel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-05-28 18:25:26 +00:00
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amd	vc/amd/pi/00630F01: Remove unused directory and code	2021-05-26 22:42:35 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT	2021-04-06 07:01:31 +00:00
google	mb/google: Move ECFW_RW setting for non-ChromeEC boards	2021-04-30 06:48:56 +00:00
intel	vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake	2021-05-28 18:25:26 +00:00
mediatek	vendor/mediatek: Add MT8195 dram initialization code	2021-05-14 04:00:38 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00