62 lines
1.9 KiB
Markdown
62 lines
1.9 KiB
Markdown
Upcoming release - coreboot 4.11
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================================
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The 4.11 release is planned for October 2019
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Update this document with changes that should be in the release
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notes.
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* Please use Markdown.
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* See the [4.9](coreboot-4.9-relnotes.md) and [4.10](coreboot-4.10-relnotes.md)
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release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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Clean Up
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--------
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Because there was only a single developer board (AMD Torpedo)
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using AGESA family 12h, and because there were multiple,
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unique Coverity issues with it, the associated vendorcode will
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be removed shortly after this release.
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Significant changes
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-------------------
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### Add significant changes here
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### `__PRE_RAM__` is deprecated
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Preprocessor use of `defined(__PRE_RAM_)` have been mostly replaced with
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`if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`.
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The remaining cases and `-D__PRE_RAM__` are to be removed soon after release.
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### `CAR_GLOBAL` is removed where possible
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For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL`
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attributes have been removed. Remaining cases from common code are to be
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removed soon after release.
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### `TSEG` and `cbmem_top()` mapping
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Significant refactoring has bee done to achieve some consistency across platforms
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and to reduce code duplication.
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### Added VBOOT support to the following platforms:
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* intel/gm45
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* intel/nehalem
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### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK:
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* intel/gm45
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* intel/nehalem
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* intel/braswell
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### Other
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* Did cleanups around TSC timer
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* Improved automatic VR configuration on SKL/KBL
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* Filled additional fields in SMBIOS type 4
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* Removed magic value replay from Intel Nehalem/ibexpeak code base
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* Added OpenSBI on RISCV platforms
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* Did more preparations for Intel TXT support
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* Did more preparations for x86_64 stage support
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* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb
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