coreboot-kgpe-d16/src
Furquan Shaikh e3a692d7da intel/apollolake: Clear TSEG reg early in bootblock
TSEG register comes out of reset with a non-zero default value. This
causes issues when cbmem_top returns non-zero value based on TSEG read
before DRAM is initialized. Thus, clear TSEG reg early in bootblock to
avoid unwanted side-effects.

Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15049
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-03 04:53:58 +02:00
..
acpi
arch SMBIOS: Implement SKU field 2016-06-02 06:24:24 +02:00
commonlib
console
cpu
device
drivers drivers/intel/fsp1_1: Update weak MRC cache routines 2016-06-02 17:15:41 +02:00
ec
include SMBIOS: Implement SKU field 2016-06-02 06:24:24 +02:00
lib cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP 2016-06-02 17:21:39 +02:00
mainboard google/reef: Select UART_FOR_CONSOLE for reef 2016-06-02 17:21:17 +02:00
northbridge
soc intel/apollolake: Clear TSEG reg early in bootblock 2016-06-03 04:53:58 +02:00
southbridge drivers/lenovo: Add hybrid graphics driver 2016-06-01 23:22:01 +02:00
superio
vendorcode
Kconfig cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP 2016-06-02 17:21:39 +02:00