Furquan Shaikh e3a692d7da intel/apollolake: Clear TSEG reg early in bootblock ... TSEG register comes out of reset with a non-zero default value. This causes issues when cbmem_top returns non-zero value based on TSEG read before DRAM is initialized. Thus, clear TSEG reg early in bootblock to avoid unwanted side-effects. Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15049 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)		2016-06-03 04:53:58 +02:00
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broadcom/cygnus	soc/*: fix uart's regwidth specification in cbtables	2016-02-21 12:26:05 +01:00
dmp/vortex86ex	dmp/vortex86ex: Merge northbridge and southbridge into soc	2016-05-05 20:06:33 +02:00
imgtec/pistachio	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
intel	intel/apollolake: Clear TSEG reg early in bootblock	2016-06-03 04:53:58 +02:00
marvell	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
mediatek/mt8173	soc/mediatek/mt8173: mt6391: vcore sleep voltage should be 0.7V	2016-05-09 08:36:57 +02:00
nvidia	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
qualcomm	Gale board: Move TPM setup function to verstage.c	2016-06-02 00:19:11 +02:00
rdc/r8610	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
rockchip	rockchip: rk3399: enable sdhci clk for emmc	2016-05-18 20:23:42 +02:00
samsung	soc/samsung: Don't compile in unused uart divider tables	2016-05-11 21:21:41 +02:00
ucb/riscv	tree: drop last paragraph of GPL copyright header	2015-10-31 21:37:39 +01:00