Subrata Banik c4986eb7f4 soc/intel/common/block: Add common chip config block ... Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-06-06 06:23:45 +00:00
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variants	soc/intel/common/block: Add common chip config block	2018-06-06 06:23:45 +00:00
acpi_tables.c
board_info.txt
bootblock.c
chromeos.c
chromeos.fmd	mb/google/octopus: Re-size flash WP_RO segment	2018-05-22 07:14:55 +00:00
dsdt.asl	mb/google/octopus: Add dptf.asl in dsdt.asl	2018-04-26 21:32:10 +00:00
ec.c
Kconfig	security/tpm: Unify the coreboot TPM software stack	2018-06-04 20:33:07 +00:00
Kconfig.name	mb/google/octopus: Enable RT5682 headset codec for BIP board	2018-06-01 16:25:13 +00:00
mainboard.c	mb/google: Get rid of device_t	2018-05-08 18:31:26 +00:00
Makefile.inc
romstage.c	mb/google/octopus: save dimm info as SMBIOS Table-17	2018-04-30 06:23:13 +00:00
smihandler.c	mb/google/octopus: Disable BT before S5 entry	2018-05-18 06:19:32 +00:00