Mariusz Szafrański f3c84024b1 mainboard/intel/harcuvar: Remove hardcoded lapic 0 from devicetree.cb ... This change follows other Intel SoCs common way to support SKUs with bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and allowing its detection at boottime. It completes support for HCV/DNV after base SoC patch: commit ba936ce5db soc/intel/denverton_ns: Ensure CPU device has a valid link Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/ "A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)." Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11 Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>		2021-08-28 21:27:46 +00:00
..
acpi
spd
acpi_tables.c
board_info.txt
boardid.c
devicetree.cb	mainboard/intel/harcuvar: Remove hardcoded lapic 0 from devicetree.cb	2021-08-28 21:27:46 +00:00
dsdt.asl
emmc.h
gpio.h
harcuvar_boardid.h
hsio.c
hsio.h
Kconfig	mb/*: Specify type of MAINBOARD_PART_NUMBER once	2021-07-26 14:05:29 +00:00
Kconfig.name
Makefile.inc	mb/intel/harcuvar: Drop build guards for ENABLE_FSP_MEMORY_DOWN	2021-02-22 07:23:36 +00:00
ramstage.c
romstage.c	mb/intel/harcuvar: Drop build guards for ENABLE_FSP_MEMORY_DOWN	2021-02-22 07:23:36 +00:00