51bbdac7d5
Currently only two devices make use of physical dev switch: stumpy, lumpy Deprecate this switch. If these devices are flashed to ToT, they may still make use of virtual dev switch, activated via recovery screen. BUG=b:124141368, b:124192753, chromium:942901 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31943 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
99 lines
2.5 KiB
C
99 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <ec/google/chromeec/ec.h>
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#include <soc/gpio.h>
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#include <soc/sata.h>
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#include "onboard.h"
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#define GPIO_SPI_WP 58
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#define GPIO_REC_MODE 12
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#define FLAG_SPI_WP 0
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#define FLAG_REC_MODE 1
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#if ENV_RAMSTAGE
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#include <boot/coreboot_tables.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{GPIO_SPI_WP, ACTIVE_HIGH,
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get_gpio(GPIO_SPI_WP), "write protect"},
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{GPIO_REC_MODE, ACTIVE_LOW,
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get_recovery_mode_switch(), "recovery"},
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{-1, ACTIVE_HIGH, 1, "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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#endif
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int get_write_protect_state(void)
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{
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
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#else
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struct device *dev = pcidev_on_root(0x1f, 2);
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#endif
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return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
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}
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int get_recovery_mode_switch(void)
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{
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
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#else
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struct device *dev = pcidev_on_root(0x1f, 2);
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#endif
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return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
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}
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void init_bootmode_straps(void)
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{
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u32 flags = 0;
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
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#else
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struct device *dev = pcidev_on_root(0x1f, 2);
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#endif
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/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
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if (get_gpio(GPIO_SPI_WP))
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flags |= (1 << FLAG_SPI_WP);
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/* Recovery: GPIO12 = RECOVERY_L, active low */
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if (!get_gpio(GPIO_REC_MODE))
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flags |= (1 << FLAG_REC_MODE);
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/* Developer: Virtual */
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pci_write_config32(dev, SATA_SP, flags);
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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