Julius Werner e57c303153 tegra124: clock: Enforce PLL constraints for VCO and CF ... This patch adds some documentation to the additional PLL divisor constraints on the intermediary VCO and CF values that we just found out about. PLLC divisors for some oscillators had to be adjusted accordingly. It also adds a new clock_get_pll_input_khz() function to replace clock_get_osc_khz() in cases where you want to factor in the built-in predivider for 38.4 and 48 MHz oscillators. BUG=None TEST=Still boots. Original-Change-Id: Ib6e026dbab9fcc50d6d81a884774ad07c7b0dbc3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194474 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 3f1f565baf100edcd486055e4317c675c882396f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I091f42bf952a4b58ef2c30586baa5bf7496fa599 Reviewed-on: http://review.coreboot.org/7768 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)		2014-12-16 23:29:16 +01:00
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tegra	tegra124: clock: Enforce PLL constraints for VCO and CF	2014-12-16 23:29:16 +01:00
tegra124	tegra124: clock: Enforce PLL constraints for VCO and CF	2014-12-16 23:29:16 +01:00
Kconfig	tegra124: Add a stub implementation of the tegra124 SOC.	2014-08-05 18:44:53 +02:00
Makefile.inc	tegra124: Add a stub implementation of the tegra124 SOC.	2014-08-05 18:44:53 +02:00