coreboot-kgpe-d16/src/mainboard/intel/bakersport_fsp
Alexandru Gagniuc 47818b4d60 fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a
mess of it, by forcing a build-time error when CONFIG_POST_IO was not
being set. fsp 1.0 boards ended 'select'ing this in their Kconfig.

Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the
"select POST_IO" from boards that have it. Instead of implementing an
ad-hoc changing post code display and a delay based on port 0xed, just
encode the FSP failure code in the POST code. Since FSP failure codes
are > 16, we can encode the failure code in the lower nibble, and theirfailing function in the upper nibble.

Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8485
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-10-06 04:09:47 +00:00
..
board_info.txt src/mainboard/*/*/board_info.txt: Added Release year for boards 2015-04-23 14:42:44 +02:00
Kconfig fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO 2015-10-06 04:09:47 +00:00
Kconfig.name kconfig: automatically include mainboards 2015-04-18 08:31:08 +02:00