coreboot-kgpe-d16/src/soc/intel/braswell
Duncan Laurie e73da80d2c braswell: Switch to using common ACPI _SWS code
Switch braswell to use the common code for filling out the NVS
data used by ACPI _SWS methods.  This code was out of date on
braswell so also update it to provide the \_GPE.SWS method.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-cyan coreboot

Change-Id: I41c2a141c15f78dc0d9482954c157f81bd0759fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c4d1ee76f337addf687ca5a9ae2da5e898c2de0
Original-Change-Id: I44424784d5d3afb06d0d58c651a9339c7b77418c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298230
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17 14:23:52 +00:00
..
acpi braswell: Switch to using common ACPI _SWS code 2015-09-17 14:23:52 +00:00
bootblock x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
include/soc braswell: Switch to using common ACPI _SWS code 2015-09-17 14:23:52 +00:00
microcode microcode: Unify rules to add microcode to CBFS once again 2015-09-07 23:51:30 +00:00
romstage fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
acpi.c fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
chip.c fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
chip.h fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
cpu.c intel/braswell: allow dirty cache line evictions for SMRAM to stick 2015-08-29 07:10:52 +00:00
elog.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
emmc.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
gfx.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
gpio.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
gpio_support.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
hda.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
iosf.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
Kconfig braswell: Switch to using common ACPI _SWS code 2015-09-17 14:23:52 +00:00
lpc_init.c Braswell: Update to end of June. 2015-07-06 18:45:23 +02:00
lpe.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
lpss.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
Makefile.inc Move final Intel chipsets with ME to intel/common/firmware 2015-09-16 14:36:01 +00:00
memmap.c intel/common: fix stage_cache_external_region() 2015-08-14 15:19:31 +02:00
northcluster.c fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
pcie.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
placeholders.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
pmutil.c Braswell: Update to end of June. 2015-07-06 18:45:23 +02:00
ramstage.c braswell: Switch to using common ACPI _SWS code 2015-09-17 14:23:52 +00:00
sata.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
scc.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
sd.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
smihandler.c braswell: Tristate CFIO 139 and CFIO 140 2015-09-08 11:48:09 +00:00
smm.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
southcluster.c Braswell: Update the ACPI tables 2015-07-06 18:44:38 +02:00
spi.c Drop "See file CREDITS..." comment 2015-09-07 15:54:50 +00:00
spi_loading.c Braswell: Add Braswell SOC support 2015-06-25 21:50:48 +02:00
tsc_freq.c Braswell: Update to end of June. 2015-07-06 18:45:23 +02:00