cbfec89037
This change properly assigns resources to the LPE (Low Power Engine for Audio) and enables ACPI mode. lpe.c was copied from intel/baytrail with a few minor adjustment for the different config structure. ACPI mode requires setting LpeAcpiModeEnable=LPE_ACPI_MODE_ENABLED and applying the patch that disables clearing gnvs. https://review.coreboot.org/#/c/14040/ Change-Id: I3fff9aa158bde88e571082642d4f985a5ae1976e Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
357 lines
10 KiB
C
357 lines
10 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2014-2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _FSP_BAYTRAIL_CHIP_H_
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#define _FSP_BAYTRAIL_CHIP_H_
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#include <arch/acpi.h>
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#include <drivers/intel/fsp1_0/fsp_values.h>
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/* The devicetree parser expects chip.h to reside directly in the path
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* specified by the devicetree. */
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struct soc_intel_fsp_baytrail_config {
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/* ***** UPD Configuration ***** */
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/* Spd addresses */
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uint8_t PcdMrcInitSPDAddr1;
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uint8_t PcdMrcInitSPDAddr2;
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#define SPD_ADDR_DEFAULT UPD_SPD_ADDR_DEFAULT
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#define SPD_ADDR_DISABLED UPD_SPD_ADDR_DISABLED
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/* SataMode
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* NOTE: These are offset by 1 to set 0 as "use default". This is so that
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* if the register value is not set in the devicetree.cb file, the default
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* value gets used. This is fixed up in the chipset_fsp_util.c code.
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*
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* 0x0 "IDE"
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* 0x1 "AHCI"
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*/
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uint8_t PcdSataMode;
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#define SATA_MODE_DEFAULT UPD_DEFAULT
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#define SATA_MODE_IDE INCREMENT_FOR_DEFAULT(0)
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#define SATA_MODE_AHCI INCREMENT_FOR_DEFAULT(1)
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/*
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* MrcInitMmioSize
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* 0x400, "1.0 GB"s
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* 0x600, "1.5 GB"
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* 0x800, "2.0 GB"
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*/
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uint16_t PcdMrcInitMmioSize;
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#define MMIO_SIZE_DEFAULT UPD_DEFAULT
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#define MMIO_SIZE_1_0_GB INCREMENT_FOR_DEFAULT(0x400)
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#define MMIO_SIZE_1_5_GB INCREMENT_FOR_DEFAULT(0x600)
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#define MMIO_SIZE_2_0_GB INCREMENT_FOR_DEFAULT(0x800)
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/*
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* eMMCBootMode
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* NOTE: These are offset by 1 to set 0 as "use default". This is so that
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* if the register value is not set in the devicetree.cb file, the default
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* value gets used. This is fixed up in the chipset_fsp_util.c code
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*
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* 0x0 "Disabled"
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* 0x1 "Auto"
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* 0x2 "eMMC 4.1"
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* 0x3 "eMMC 4.5"
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*/
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uint8_t PcdeMMCBootMode;
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#define EMMC_USE_DEFAULT UPD_DEFAULT
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#define EMMC_DISABLED UPD_DISABLE
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#define EMMC_AUTO INCREMENT_FOR_DEFAULT(1)
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#define EMMC_4_1 INCREMENT_FOR_DEFAULT(2)
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#define EMMC_4_5 INCREMENT_FOR_DEFAULT(3)
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#define EMMC_FOLLOWS_DEVICETREE UPD_USE_DEVICETREE
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/*
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* IgdDvmt50PreAlloc
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* 0x01, "32 MB"
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* 0x02, "64 MB"
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* 0x03, "96 MB"
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* 0x04, "128 MB"
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* 0x05, "160 MB"
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* 0x06, "192 MB"
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* 0x07, "224 MB"
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* 0x08, "256 MB"
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* 0x09, "288 MB"
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* 0x0A, "320 MB"
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* 0x0B, "352 MB"
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* 0x0C, "384 MB"
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* 0x0D, "416 MB"
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* 0x0E, "448 MB"
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* 0x0F, "480 MB"
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* 0x10, "512 MB"
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*/
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uint8_t PcdIgdDvmt50PreAlloc;
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#define IGD_MEMSIZE_DEFAULT UPD_DEFAULT
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#define IGD_MEMSIZE_32MB INCREMENT_FOR_DEFAULT(0x01)
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#define IGD_MEMSIZE_64MB INCREMENT_FOR_DEFAULT(0x02)
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#define IGD_MEMSIZE_96MB INCREMENT_FOR_DEFAULT(0x03)
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#define IGD_MEMSIZE_128MB INCREMENT_FOR_DEFAULT(0x04)
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#define IGD_MEMSIZE_160MB INCREMENT_FOR_DEFAULT(0x05)
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#define IGD_MEMSIZE_192MB INCREMENT_FOR_DEFAULT(0x06)
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#define IGD_MEMSIZE_224MB INCREMENT_FOR_DEFAULT(0x07)
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#define IGD_MEMSIZE_256MB INCREMENT_FOR_DEFAULT(0x08)
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#define IGD_MEMSIZE_288MB INCREMENT_FOR_DEFAULT(0x09)
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#define IGD_MEMSIZE_320MB INCREMENT_FOR_DEFAULT(0x0A)
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#define IGD_MEMSIZE_352MB INCREMENT_FOR_DEFAULT(0x0B)
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#define IGD_MEMSIZE_384MB INCREMENT_FOR_DEFAULT(0x0C)
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#define IGD_MEMSIZE_416MB INCREMENT_FOR_DEFAULT(0x0D)
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#define IGD_MEMSIZE_448MB INCREMENT_FOR_DEFAULT(0x0E)
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#define IGD_MEMSIZE_480MB INCREMENT_FOR_DEFAULT(0x0F)
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#define IGD_MEMSIZE_512MB INCREMENT_FOR_DEFAULT(0x10)
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#define IGD_MEMSIZE_MULTIPLIER 32
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/*
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* Selection 0x1 , "128 MB"
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* Selection 0x2 , "256 MB"
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* Selection 0x3 , "512 MB"
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*/
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uint8_t PcdApertureSize;
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#define APERTURE_SIZE_DEFAULT UPD_DEFAULT
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#define APERTURE_SIZE_128MB INCREMENT_FOR_DEFAULT(1)
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#define APERTURE_SIZE_256MB INCREMENT_FOR_DEFAULT(2)
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#define APERTURE_SIZE_512MB INCREMENT_FOR_DEFAULT(3)
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#define APERTURE_SIZE_BASE 64
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/*
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* Selection 0x1 , "1 MB"
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* Selection 0x2 , "2 MB"
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*/
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uint8_t PcdGttSize;
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#define GTT_SIZE_DEFAULT UPD_DEFAULT
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#define GTT_SIZE_1MB INCREMENT_FOR_DEFAULT(1)
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#define GTT_SIZE_2MB INCREMENT_FOR_DEFAULT(2)
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/*
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* Enable PCI Mode for LPSS SIO devices.
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* If disabled, LPSS SIO devices will run in ACPI mode.
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*/
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uint8_t PcdLpssSioEnablePciMode;
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#define LPSS_PCI_MODE_DEFAULT UPD_DEFAULT
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#define LPSS_PCI_MODE_DISABLE UPD_DISABLE
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#define LPSS_PCI_MODE_ENABLE UPD_ENABLE
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/* modifiers for various enables */
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uint8_t AzaliaAutoEnable;
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#define AZALIA_FOLLOWS_DEVICETREE UPD_USE_DEVICETREE
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#define AZALIA_FSP_AUTO_ENABLE UPD_ENABLE
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uint8_t LpeAcpiModeEnable;
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#define LPE_ACPI_MODE_DISABLED UPD_DISABLE
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#define LPE_ACPI_MODE_ENABLED UPD_ENABLE
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uint32_t SerialDebugPortAddress;
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#define SerialDebugPortAddress_DEFAULT UPD_DEFAULT
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uint8_t SerialDebugPortType;
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#define SERIAL_DEBUG_PORT_DEFAULT UPD_DEFAULT
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#define SERIAL_DEBUG_PORT_TYPE_NONE INCREMENT_FOR_DEFAULT(0)
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#define SERIAL_DEBUG_PORT_TYPE_IO INCREMENT_FOR_DEFAULT(1)
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#define SERIAL_DEBUG_PORT_TYPE_MMIO INCREMENT_FOR_DEFAULT(2)
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uint8_t PcdMrcDebugMsg;
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#define MRC_DEBUG_MSG_DEFAULT UPD_DEFAULT
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#define MRC_DEBUG_MSG_DISABLE UPD_DISABLE
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#define MRC_DEBUG_MSG_ENABLE UPD_ENABLE
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uint8_t PcdSccEnablePciMode;
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#define SCC_PCI_MODE_DEFAULT UPD_DEFAULT
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#define SCC_PCI_MODE_DISABLE UPD_DISABLE
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#define SCC_PCI_MODE_ENABLE UPD_ENABLE
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uint8_t IgdRenderStandby;
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#define IGD_RENDER_STANDBY_DEFAULT UPD_DEFAULT
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#define IGD_RENDER_STANDBY_DISABLE UPD_DISABLE
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#define IGD_RENDER_STANDBY_ENABLE UPD_ENABLE
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uint8_t TxeUmaEnable;
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#define TXE_UMA_DEFAULT UPD_DEFAULT
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#define TXE_UMA_DISABLE UPD_DISABLE
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#define TXE_UMA_ENABLE UPD_ENABLE
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/*
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* PcdOsSelection
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* Selection 0x1 , "Android"
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* Selection 0x4 , "Linux OS"
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*/
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uint8_t PcdOsSelection;
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#define OS_SELECTION_DEFAULT UPD_DEFAULT
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#define OS_SELECTION_ANDROID INCREMENT_FOR_DEFAULT(1)
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#define OS_SELECTION_LINUX INCREMENT_FOR_DEFAULT(4)
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/* PcdEMMC45DDR50Enabled */
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uint8_t PcdEMMC45DDR50Enabled;
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#define EMMC45_DDR50_DEFAULT UPD_DEFAULT
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#define EMMC45_DDR50_DISABLE UPD_DISABLE
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#define EMMC45_DDR50_ENABLE UPD_ENABLE
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/* PcdEMMC45HS200Enabled */
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uint8_t PcdEMMC45HS200Enabled;
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#define EMMC45_HS200_DEFAULT UPD_DEFAULT
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#define EMMC45_HS200_DISABLE UPD_DISABLE
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#define EMMC45_HS200_ENABLE UPD_ENABLE
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/* PcdEMMC45RetuneTimerValue */
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uint8_t PcdEMMC45RetuneTimerValue;
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#define EMMC45_RETURN_TIMER_DEFAULT UPD_DEFAULT
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/* PcdEnableIgd */
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uint8_t PcdEnableIgd;
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#define ENABLE_IGD_DEFAULT UPD_DEFAULT
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#define ENABLE_IGD_DISABLE UPD_DISABLE
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#define ENABLE_IGD_ENABLE UPD_ENABLE
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/* AutoSelfRefreshEnable */
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uint8_t AutoSelfRefreshEnable;
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#define AUTO_SELF_REFRESH_DEFAULT UPD_DEFAULT
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#define AUTO_SELF_REFRESH_DISABLE UPD_DISABLE
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#define AUTO_SELF_REFRESH_ENABLE UPD_ENABLE
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/* APTaskTimeoutCnt */
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uint16_t APTaskTimeoutCnt;
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#define AP_TASK_TIMEOUT_CNT_DEFAULT UPD_DEFAULT
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/* Memory down data */
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uint8_t EnableMemoryDown;
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#define MEMORY_DOWN_DEFAULT UPD_DEFAULT
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#define MEMORY_DOWN_DISABLE UPD_DISABLE
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#define MEMORY_DOWN_ENABLE UPD_ENABLE
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/*
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* PcdDRAMSpeed
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* Selection 0x0 , "800 MHz"
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* Selection 0x1 , "1066 MHz"
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* Selection 0x2 , "1333 MHz"
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* Selection 0x3 , "1600 MHz"
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*/
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uint8_t DRAMSpeed;
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#define DRAM_SPEED_DEFAULT UPD_DEFAULT
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#define DRAM_SPEED_800MHZ INCREMENT_FOR_DEFAULT(0)
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#define DRAM_SPEED_1066MHZ INCREMENT_FOR_DEFAULT(1)
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#define DRAM_SPEED_1333MHZ INCREMENT_FOR_DEFAULT(2)
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#define DRAM_SPEED_1600MHZ INCREMENT_FOR_DEFAULT(3)
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/*
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* PcdDRAMType
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* Selection 0x0 , "DDR3"
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* Selection 0x1 , "DDR3L"
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* Selection 0x2 , "DDR3U"
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* Selection 0x4 , "LPDDR2"
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* Selection 0x5 , "LPDDR3"
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* Selection 0x6 , "DDR4"
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*/
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uint8_t DRAMType;
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#define DRAM_TYPE_DEFAULT UPD_DEFAULT
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#define DRAM_TYPE_DDR3 INCREMENT_FOR_DEFAULT(0)
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#define DRAM_TYPE_DDR3L INCREMENT_FOR_DEFAULT(1)
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uint8_t DIMM0Enable;
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#define DIMM0_ENABLE_DEFAULT UPD_DEFAULT
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#define DIMM0_DISABLE UPD_DISABLE
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#define DIMM0_ENABLE UPD_ENABLE
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uint8_t DIMM1Enable;
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#define DIMM1_ENABLE_DEFAULT UPD_DEFAULT
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#define DIMM1_DISABLE UPD_DISABLE
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#define DIMM1_ENABLE UPD_ENABLE
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/*
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* PcdDIMMDWidth
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* Selection 0x0 , "x8"
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* Selection 0x1 , "x16"
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* Selection 0x2 , "x32"
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*/
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uint8_t DIMMDWidth;
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#define DIMM_DWIDTH_DEFAULT UPD_DEFAULT
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#define DIMM_DWIDTH_X8 INCREMENT_FOR_DEFAULT(0)
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#define DIMM_DWIDTH_X16 INCREMENT_FOR_DEFAULT(1)
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#define DIMM_DWIDTH_X32 INCREMENT_FOR_DEFAULT(2)
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/*
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* PcdDIMMDensity
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* Selection 0x0 , "1 Gbit"
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* Selection 0x1 , "2 Gbit"
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* Selection 0x2 , "4 Gbit"
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* Selection 0x3 , "8 Gbit"
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*/
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uint8_t DIMMDensity;
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#define DIMM_DENSITY_DEFAULT UPD_DEFAULT
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#define DIMM_DENSITY_1G_BIT INCREMENT_FOR_DEFAULT(0)
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#define DIMM_DENSITY_2G_BIT INCREMENT_FOR_DEFAULT(1)
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#define DIMM_DENSITY_4G_BIT INCREMENT_FOR_DEFAULT(2)
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#define DIMM_DENSITY_8G_BIT INCREMENT_FOR_DEFAULT(3)
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/*
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* PcdDIMMBusWidth
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* Selection 0x0 , "8 bits"
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* Selection 0x1 , "16 bits"
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* Selection 0x2 , "32 bits"
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* Selection 0x3 , "64 bits"
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*/
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uint8_t DIMMBusWidth;
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#define DIMM_BUS_WIDTH_DEFAULT UPD_DEFAULT
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#define DIMM_BUS_WIDTH_8BIT INCREMENT_FOR_DEFAULT(0)
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#define DIMM_BUS_WIDTH_16BIT INCREMENT_FOR_DEFAULT(1)
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#define DIMM_BUS_WIDTH_32BIT INCREMENT_FOR_DEFAULT(2)
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#define DIMM_BUS_WIDTH_64BIT INCREMENT_FOR_DEFAULT(3)
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/*
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* PcdDIMMSides
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* Selection 0x0 , "1 Ranks"
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* Selection 0x1 , "2 Ranks"
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*/
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uint8_t DIMMSides;
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#define DIMM_SIDES_DEFAULT UPD_DEFAULT
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#define DIMM_SIDES_1RANK INCREMENT_FOR_DEFAULT(0)
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#define DIMM_SIDES_2RANK INCREMENT_FOR_DEFAULT(1)
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uint8_t DIMMtCL;
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#define DIMM_TCL_DEFAULT UPD_DEFAULT
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uint8_t DIMMtRPtRCD;
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#define DIMM_TRP_TRCD_DEFAULT UPD_DEFAULT
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uint8_t DIMMtWR;
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#define DIMM_TWR_DEFAULT UPD_DEFAULT
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uint8_t DIMMtWTR;
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#define DIMM_TWTR_DEFAULT UPD_DEFAULT
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uint8_t DIMMtRRD;
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#define DIMM_TRRD_DEFAULT UPD_DEFAULT
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uint8_t DIMMtRTP;
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#define DIMM_TRTP_DEFAULT UPD_DEFAULT
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uint8_t DIMMtFAW;
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#define DIMM_TFAW_DEFAULT UPD_DEFAULT
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/* LPE Audio Clock configuration. */
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int lpe_codec_clk_freq; /* 19 or 25 are valid. */
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int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
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/* ***** ACPI configuration ***** */
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/* Options for these are in src/arch/x86/include/arch/acpi.h */
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uint8_t fadt_pm_profile;
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uint16_t fadt_boot_arch;
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};
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extern struct chip_operations soc_intel_fsp_baytrail_ops;
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#endif /* _FSP_BAYTRAIL_CHIP_H_ */
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