Xavi Drudis Ferran 19245c94c8 Improving BKDG implementation of P-states, ... CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Factor out some common expressions. Add an error message when coreboots hangs waiting for a pstate that never comes (it happened to me), and throw some paranoia at it for good mesure. If I understood BKDG fam10 CPUs never need a software initiated vid transition, because the hardware knows what to do when you just request a Pstate change if the cpu is properly configured. In fact unifying a little what PVI and SVI do was better for my board (SVI). So I drop transitionVid, which I didn't understand either (why did it have a case for PVI if it is never called for PVI ? Why did the PVI case distinguigh cpu or nb when PVI is theoretically single voltage plane ? ). Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2011-02-28 03:02:40 +00:00
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mct	Fix some settings fo AMD MCT. It is based on BIOS test suite.	2011-01-06 02:18:12 +00:00
mct_ddr3	For Cx, each ChipSel need to be sent MR command.	2011-01-20 02:09:24 +00:00
wrappers	Improving BKDG implementation of P-states,	2011-02-28 03:02:40 +00:00
amddefs.h	Improving BKDG implementation of P-states,	2011-02-28 02:33:59 +00:00