Andrey Petrov e976bd4469 soc/intel/apollolake: Enable LPC bus interface ... This adds early LPC setup in bootblock (for Chrome EC) as well as late (ramstage) IO decode/sirq enable. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14469 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-04-28 05:38:34 +02:00
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apollolake	soc/intel/apollolake: Enable LPC bus interface	2016-04-28 05:38:34 +02:00
baytrail	soc/intel: Update license headers	2016-04-14 16:54:33 +02:00
braswell	soc/intel: Update license headers	2016-04-14 16:54:33 +02:00
broadwell	soc/intel: Update license headers	2016-04-14 16:54:33 +02:00
common	src/soc/intel/common: Fix CID 1295499, remove dead code	2016-04-13 07:00:27 +02:00
fsp_baytrail	intel/fsp_baytrail: Eliminate warning about missing set_resources	2016-04-16 02:04:41 +02:00
fsp_broadwell_de	intel/fsp_broadwell_de: fix SPD CBFS file type	2016-04-20 23:37:29 +02:00
quark	soc/intel/quark: Fix MTRR reads	2016-04-22 17:45:03 +02:00
skylake	soc/intel: Update license headers	2016-04-14 16:54:33 +02:00