214 lines
6.7 KiB
Markdown
214 lines
6.7 KiB
Markdown
Upcoming release - coreboot 4.11
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================================
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coreboot 4.11 was released on November 19th.
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This release cycle was a bit shorter to get closer to our regular
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schedule of releasing in spring and autumn.
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Since 4.10 there were 1630 new commits by over 130 developers.
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Of these, about 30 contributed to coreboot for the first time.
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Thank you to all contributors who made 4.11 what it is and welcome
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to the project to all new contributors!
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Clean Up
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--------
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The past few months saw lots of cleanup across the source tree:
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The included headers in source files were stripped down to avoid reading
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unused headers, and unused code fragments, duplicate preprocessor symbols
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and configuration options were eliminated. Even ACPI got its share
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of attention, making our tables and bytecode more standards compliant
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than ever.
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The code across Intel's chipsets was unified some more into drivers for
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common function blocks, an effort we're more confident will succeed now
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that Intel itself is driving it.
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Chipset work
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------------
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Most activity in the last couple months was on Intel support,
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specifically the Kaby Lake and Cannon Lake drivers were extended
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for the generations following them.
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On ARM, the Mediatek 8173 chipset support saw significant work while
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the AMD side worked on getting Picasso support in.
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But everything else also saw some action, the relatively old
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(e.g. Intel GM45, Via VX900), the tiny (RISC-V) and the obscure
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(Quark).
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Verified Boot
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-------------
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The vboot feature that Chromebooks brought into coreboot was extended
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to work on devices that weren't specially adapted for it: In addition
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to its original device family it's now supported on various Lenovo
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laptops, Open Compute Project systems and Siemens industrial machines.
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Eltan's support for measured boot continues to be integrated with
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vboot, sharing data structures and generally working together where
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possible.
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New devices
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-----------
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With 4.11 there's the beginning of support for Intel Tiger Lake and
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Qualcomm's SC7180 SoCs, while we removed the unmaintained support
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for Allwinner's A10 SoC.
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There are also 25 new mainboards in our tree:
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* AMD PADMELON
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* ASUS P5QL-EM
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* EMULATION QEMU-AARCH64
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* GOOGLE AKEMI
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* GOOGLE ARCADA CML
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* GOOGLE DAMU
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* GOOGLE DOOD
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* GOOGLE DRALLION
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* GOOGLE DRATINI
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* GOOGLE JACUZZI
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* GOOGLE JUNIPER
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* GOOGLE KAKADU
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* GOOGLE KAPPA
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* GOOGLE PUFF
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* GOOGLE SARIEN CML
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* GOOGLE TREEYA
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* GOOGLE TROGDOR
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* LENOVO R60
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* LENOVO T410
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* LENOVO THINKPAD T440P
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* LENOVO X301
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* RAZER BLADE-STEALTH KBL
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* SIEMENS MC-APL6
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* SUPERMICRO X11SSH-TF
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* SUPERMICRO X11SSM-F
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In addition to the Cubieboard (which uses the A10 SoC), we also
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removed Google Hatch WHL.
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Deprecations
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------------
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Because there was only a single developer board (AMD Torpedo)
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using AGESA family 12h, and because there were multiple,
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unique Coverity issues with it, the associated vendorcode will
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be removed shortly after this release.
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Support for the MIPS architecture will also be removed shortly after
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this release as the only board in the tree was a discontinued development
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board and no other work has picked up MIPS support, so it's very likely
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broken already.
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After more than a year of planning and following the announcement in
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coreboot 4.10, platforms not using relocatable ramstage, a C bootblock
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and, on systems using Cache as RAM, a postcar stage, won't be supported
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going forward.
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Significant changes
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-------------------
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### `__PRE_RAM__` is deprecated
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Preprocessor use of `defined(__PRE_RAM__)` have been mostly replaced with
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`if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`.
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The remaining cases and `-D__PRE_RAM__` are to be removed soon after release.
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### `__BOOTBLOCK__` et.al. are converted
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This applies to all `ENV_xxx` definitions found in `<rules.h>`.
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Write code without preprocessor directives whenever possible, replacing
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`#ifdef __BOOTBLOCK__` with `if (ENV_BOOTBLOCK)`
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In cases where preprocessor is needed use `#if ENV_BOOTBLOCK` instead.
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### `CAR_GLOBAL` is removed where possible
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For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL`
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attributes have been removed. Remaining cases from common code are to be
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removed soon after release.
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### `TSEG` and `cbmem_top()` mapping
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Significant refactoring has bee done to achieve some consistency across platforms
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and to reduce code duplication.
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### Build system amenities ###
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The build system now has an `all` class of source files to remove the need to
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list source files for each and every source class (romstage, ramstage, ...)
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The site-local/ mechanism became more robust.
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### Stricter coding standards to improve security ###
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The build now fails on variable length arrays (that make it way too easy to
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smash a stack) and case statements falling through without a note that it is
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intentional.
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### Shorter file headers ###
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This project is still under way, but we started moving author information
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from individual files into the global AUTHORS file (and there's the git
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history for more details).
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In the future, we also want to replace the license headers (lots of lines)
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in each file with spdx identifiers (one line) and so we added a LICENSES/
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directory that contains the full text of all the licenses that are used
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throughout our tree.
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### Variant creation scripts ###
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To ease the creation of variant boards, `util/mainboard/` now contains
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scripts to generate a new variant to a given board. These are still
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specific to google/hatch at this time, but they're written with the idea
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of becoming more generally useful.
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### Payloads ###
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Payload integration has been updated, coreinfo learned to cope with
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UPPER CASE commands and libpayload knows how to deal with USB3 hubs.
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### Added VBOOT support to the following platforms:
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* intel/gm45
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* intel/nehalem
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### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK:
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* intel/i945
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* intel/x4x
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* intel/gm45
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* intel/nehalem
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* intel/sandybridge
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* intel/braswell
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### libgfxinit ###
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Most notable, dynamic CDClk configuration was added to libgfxinit,
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to support higher resolution displays without changes in the static
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configuration. It also received some fixes for better DP and eDP
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compatibility, better error recovery for Intel's fickle GMBus and
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updated platform support:
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* Correct HDMI clock limit for G45.
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* DP support for Ibex Peak (Ironlake graphics).
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* Fixed scaling on eDP for Broadwell.
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* Support for ULX variants of Haswell and later.
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* Support for Kaby, Amber, Coffee and Whiskey Lake.
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### Other
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* Did cleanups around TSC timer
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* Improved automatic VR configuration on SKL/KBL
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* Filled additional fields in SMBIOS type 4
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* Removed magic value replay from Intel Nehalem/ibexpeak code base
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* Added OpenSBI on RISCV platforms
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* Did more preparations for Intel TXT support
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* Did more preparations for x86_64 stage support
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* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb
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