211 lines
6.5 KiB
Markdown
211 lines
6.5 KiB
Markdown
# Driver Devicetree Entries
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Let's take a look at an example entry from
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``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
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```
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
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register "wake" = "GPE0_DW0_21"
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device i2c 15 on end
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end
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end # I2C #0
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```
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When this entry is processed during ramstage, it will create a device in the
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ACPI SSDT table (all devices in devicetrees end up in the SSDT table). The ACPI
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generation routines in coreboot actually generate the raw bytecode that
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represents the device's structure, but looking at ASL code is easier to
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understand; see below for what the disassembled bytecode looks like:
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```
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Scope (\_SB.PCI0.I2C0)
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{
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Device (D015)
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{
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Name (_HID, "ELAN0000") // _HID: Hardware ID
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Name (_UID, Zero) // _UID: Unique ID
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Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
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Method (_STA, 0, NotSerialized) // _STA: Status
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{
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Return (0x0F)
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}
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
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AddressingMode7Bit, "\\_SB.PCI0.I2C0",
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0x00, ResourceConsumer, , Exclusive, )
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Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
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{
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0x0000002D,
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}
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})
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Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT) // _S0W: S0 Device Wake State
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Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
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{
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0x15, // GPE #21
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0x03 // Sleep state S3
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})
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}
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}
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```
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You can see it generates _HID, _UID, _DDN, _STA, _CRS, _S0W, and _PRW
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names/methods in the Device's scope.
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## Utilizing a device driver
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The device driver must be enabled for your build. There will be a CONFIG option
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in the Kconfig file in the directory that the driver is in (e.g.,
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``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
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CONFIG_DRIVERS_I2C_GENERIC). The config option will need to be added to your
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mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
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to be compiled into your build.
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## Diving into the above example:
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Let's take a look at how the devicetree language corresponds to the generated
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ASL.
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First, note this:
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```
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chip drivers/i2c/generic
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```
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This means that the device driver we're using has a corresponding structure,
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located at ``src/drivers/i2c/generic/chip.h``, named **struct
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drivers_i2c_generic_config** and it contains many properties you can specify to
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be included in the ACPI table.
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### hid
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```
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register "hid" = ""ELAN0000""
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```
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This corresponds to **const char *hid** in the struct. In the ACPI ASL, it
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translates to:
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```
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Name (_HID, "ELAN0000") // _HID: Hardware ID
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```
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under the device. **This property is used to match the device to its driver
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during enumeration in the OS.**
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### desc
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```
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register "desc" = ""ELAN Touchpad""
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```
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corresponds to **const char *desc** and in ASL:
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```
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Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
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```
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### irq
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It also adds the interrupt,
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```
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Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
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{
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0x0000002D,
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}
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```
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which comes from:
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```
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
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```
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The GPIO pin IRQ settings control the "Level", "ActiveLow", and
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"ExclusiveAndWake" settings seen above (level means it is a level-triggered
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interrupt as opposed to edge-triggered; active low means the interrupt is
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triggered when the signal is low).
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Note that the ACPI_IRQ_WAKE_LEVEL_LOW macro informs the platform that the GPIO
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will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
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source. Also note that the IRQ names are SoC-specific, and you will need to
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find the names in your SoC's header file. The ACPI_* macros are defined in
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``src/arch/x86/include/acpi/acpi_device.h``.
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Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
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This is often done in a mainboard-specific file named ``gpio.c``.
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### wake
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The last register is:
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```
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register "wake" = "GPE0_DW0_21"
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```
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which indicates that the method of waking the system using the touchpad will be
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through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
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this example. The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
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elsewhere in the devicetree.
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The last bit of the definition of that device includes:
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```
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device i2c 15 on end
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```
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which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
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meaning it will be exposed in the ACPI table. The PCI device that the
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controller is located in determines which I2C bus the device is expected to be
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found on. In this example, this is I2C bus 0. This also determines the ACPI
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"Scope" that the device names and methods will live under, in this case
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"\_SB.PCI0.I2C0".
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## Other auto-generated names
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(see [ACPI specification
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6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
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for more details on ACPI methods)
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### _S0W (S0 Device Wake State)
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_S0W indicates the deepest S0 sleep state this device can wake itself from,
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which in this case is ACPI_DEVICE_SLEEP_D3_HOT, representing _D3hot_.
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### _PRW (Power Resources for Wake)
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_PRW indicates the power resources and events required for wake. There are no
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dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
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as well as the deepest sleep state supporting waking the system (3), which is
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S3.
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### _STA (Status)
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The _STA method is generated automatically, and its values, 0xF, indicates the
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following:
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Bit [0] – Set if the device is present.
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Bit [1] – Set if the device is enabled and decoding its resources.
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Bit [2] – Set if the device should be shown in the UI.
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Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
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### _CRS (Current resource settings)
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The _CRS method is generated automatically, as the driver knows it is an I2C
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controller, and so specifies how to configure the controller for proper
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operation with the touchpad.
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```
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
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AddressingMode7Bit, "\\_SB.PCI0.I2C0",
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0x00, ResourceConsumer, , Exclusive, )
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```
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## Notes
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- **All devices in devicetrees end up in the SSDT table, and are generated in
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coreboot's ramstage**
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